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5 Runtime Self-reconstruction for Tolerating Software/Hardware Faults Increment from Aging

5 Runtime Self-reconstruction for Tolerating Software/Hardware Faults Increment from Aging

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6.5.2



Tolerating Soft/Hard Faults with Runtime

Self-reconstruction



6.5.2.1



Concept



Most of the conventional methods mentioned in the last section only tolerate a few

kinds of single-event soft errors and one type of permanent error, so we thought that

they cannot sustain enough reliability under future ultimately scaled semiconductor

process technology. To alleviate this problem, DARA (Dynamic Adaptive redundant Architecture), a processor architecture we propose, utilizes quick error

detection and runtime self-reconstruction. DARA can apply recover operation

before the processor fails by cumulating multiple soft errors. Also, DARA can

alleviate multiple hard errors by cutting off a failed core after a permanent error has

been detected and adding a healthy core. Furthermore, by utilizing runtime

self-reconstruction effectively, DARA can self-reconfigure from TMR into DMR

execution keeping precise processor status after a permanent error has been

detected. This feature gives average power consumption reduction, restraining

degradation of spare resources by hot standby (e.g., NBTI), and reducing resources

for dependability by sharing spare resources under multicore organization.

Figure 6.32 shows the concept of DARA and Fig. 6.33 shows the outline of the

pipeline-stage-level modular execution by carving out a part of the pipeline stage.

DARA employs multicore organization designed with multiple modular redundancy configurations in mind. Each core is equipped with the following functions:

• Comparator for error detection

• Inter-core communication path connected to the comparator for modular

execution

• Error recovery administrator which summarizes discord result from the

comparator

• Partial register value protection by parity for precise processor status under

dynamic DMR to TMR expansion.

In the current implementation, we utilized 6-stage pipeline stage organization

which consists of instruction fetch (IF), instruction decode (ID), register read (RR),

Data in

Compare



Disabled core(VDD gating)



Pipeline module



IF ID RR EX MA WB



Enabled core



Data out



TMR pair



DMR pair



1. Normal execution



?



?



?



2. Detect failed core

with temporal TMR



Fig. 6.32 DARA processor core and self-reconstruction



DMR pair



3. Cut off detected

failed core



6 Time-Dependent Degradation in Device Characteristics …

Pipeline register



Pipeline register



To right edge



Register

file



=

error?



Pipeline register



Register

file



Pipeline register



From left edge



(From left edge)



=



=



error?



Pipeline register



To right edge



235



Register

file



Pipeline register



From left edge



=

ALU

error?



(From left edge)



=

ALU



error?



=

ALU



error?



error?



Fig. 6.33 Modular status and error detection in each stage



execution (EX), memory access (MA), and write back (WB). By parallelizing this

processor core, we can organize DMR/TMR organization. The processor core can

operate alone if we do not require high reliability. We have to accord some area

overhead coming from the additional circuit for comparing the processor core

without reliability. Note that parities which are added to some registers improve

reliability even if the processor core operates alone.



6.5.2.2



DMR Operation



By combining two processor cores described in the previous section, we can

achieve DMR organization. Blocks and buses delineated in solid lines in Fig. 6.33

show active part in DMR organization. Outputs of each stage are once stored in

pipeline register, and compared to the next clock cycle. The comparator and

re-execution controller are built-in individual cores, being duplicated as well. So,

DARA can continue correct operation even if error (especially permanent error like

stack-at-0 fault) has occurred in those parts.

Recovery from a detected error is done like recovery from branch misprediction.

The processor sends Program Counter value which is existing beside the instruction

in error-detected stage to the Program Counter register of IF stage. After that, the

processor restarts with instruction fetch from failed instruction. Under this procedure, there is a possibility that another error takes place. To treat this problem, we

keep precise status before re-execution has started in the pipeline and realize

“re-execution of re-execution procedure” in DARA. In case of re-execution of the

instruction which updates multiple register value, we cannot achieve precise

re-execution with above simple re-execution if the instruction updates a part of

register values. Let us consider the instruction which increments base register value

after memory read as an example. Generally, memory read requires a longer time

than a register value increment so that the order of the register value update

becomes “base register update” and “store memory read result” order. In this case,

if an error occurs under memory read, the base register value has already updated so



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that the processor status becomes wrong if the processor updates the base register

value again. To resolve this problem, we introduced instruction decomposition and

sub Program Counter value to achieve individual recover operation. Above

instruction is decomposed into memory read sub instruction and base register value

increment sub-instruction by this scheme and achieve recover operation from

individual sub Program Counter value allocated to individual sub instructions.



6.5.2.3



DTMR Operation



DARA allows dynamic DMR to TMR expansion so that DARA can migrate into

TMR mode to alleviate permanent error by adding one processor core after an error

has been detected under DMR mode. We call counter permanent error organization

based on above idea as DARA-DTMR organization.

When a permanent error has occurred in DMR mode shown in the previous

section, the permanent error has been observed as a series of soft errors that occur

too frequently. In this case, first, DARA attaches one processor core which has a

copy of the correct processor status and configures a TMR organization (add dotted

line part in Fig. 6.33). Then, DARA starts re-execution and identifies healthy cores

that output the same result. The left one core is treated as a broken core and is

detached as broken so that the system migrates into DMR mode again (Fig. 6.32).

This TMR mode migration requires several hundreds of cycles because it requires

healthy register value transmission to the attached core. On the other hand,

detaching a broken core only requires several cycles including one instruction

re-execution for the broken core detection because it does not require data transmission. It only requires identification of the DMR pair which DARA still utilize.

In DTMR organization, DARA does not supply power to the third core until a

permanent error has been detected. By this characteristic, DARA can reduce

average power consumption, subdue degradation (due, e.g., to NBTI) of spare

resources by shutting down the power supply, and sharing the spare resources in

multicore operation. Note that if we cannot tolerate overhead under DMR to TMR

expansion (e.g., real-time applications), we can choose full-time TMR operation in

DARA. DARA does not require OS support under re-execution and reconstruction

procedure. So, we (or OS) only indicate required dependability (e.g., DMR, DTMR,

full-time TMR, etc.) by the configuration of the special register value.



6.5.3



Evaluation and Discussion



6.5.3.1



Circuit Area



DARA contains a comparator and an additional data path in each processor core

module so that it gives additional area overhead. To evaluate this overhead, we

implemented DARA with Hitachi/Renesas SH-2 instruction set. The design is



6 Time-Dependent Degradation in Device Characteristics …



237



synthesized by Synopsis Design Compiler and Rohm 180 nm logic cell library to

evaluate the area. In this implementation, we implement low-capacity L1 cache to

the module itself and implement ECC to register file and caches to keep precise

value.

If we assume the area of a no-counter error processor core to be 100%, the area

of a core in DARA is 135%, DMR organization 217%, and TMR organization

298%, respectively. The reason that that DMR/TMR organization does not become

an integral multiple of the one core of DARA comes from the area of L1 cache

which is not modular because it is covered with ECC and multi-porting. Because of

ECC-covered cache and registers, 61% of the circuit is covered from errors. We

cannot achieve 100% cover rate because we could not eliminate stack-at-0 fault to

the circuits which indicate re-execution. The DARA-DTMR organization uses

TMR upon permanent error detection. So, if we assume that the power consumption

increases in proportion to the area, DARA-DTMR can tolerate permanent error with

72% power consumption of the traditional TMR organization.



6.5.3.2



Error Tolerance Under Alpha Particle Irradiation



To evaluate high-frequency soft error, we executed each benchmark of Stanford

Benchmark Suite for 1000 times under 1.25 V supply voltage and alpha particle

irradiation from Am241/3Mq alpha particle source (Fig. 6.34). Figure 6.35 shows

the number of execution cycles including re-execution operation. The horizontal

axis shows benchmarks, the line chart (with right axis) shows average and distribution of execution cycles, and the bar chart shows the average and distribution of

number of re-execution operation. The re-execution operation occurs 0.34 per

second in average. Due to architectural vulnerability factor (AVF) difference



DARA chip



Show chip surface for alpha particle irradiation



DARA

DARA-DFF

BCDMR



Place alpha particle source to chip surface

Alpha particle source(Am241)



Fig. 6.34 Manufactured DARA chip and alpha particle irradiation environment



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Fig. 6.35 Execution cycles and number of re-execution under alpha particle irradiation



between benchmark programs, the frequencies of errors differ between benchmark

programs. Typically, AVF comes from instruction mix of the benchmark program

and we found that the Puzzle benchmark contains comparatively many vulnerable

instructions. AVF also affects re-execution operation so that the distribution of the

execution cycle differs between benchmark programs that have similar error rates

and average execution cycles.



6.5.4



Conclusion



Under the concept that utilizes self-reconstruction to tolerate soft error and permanent error, we have proposed DARA architecture and evaluated it with trial

manufacturing and alpha particle irradiation. The results show that DARA-DMR

organization works correctly under high soft error rate environment. There are

several processor levels or ALU level DMR or TMR implementation. But DARA

gives further cost-effectiveness and dependability by dynamically reconstructing its

organization under required dependability and given resources.



6 Time-Dependent Degradation in Device Characteristics …



239



References

1. R. Degraeve, G. Groeseneken, R. Bellens, J.L. Ogier, M. Depas, P.J. Roussel, H.E. Maes,

New insights in the relation between electron trap generation and the statistical properties of

oxide breakdown. IEEE Trans. Electron Devices 45(4), 904–911 (1998)

2. B. Kaczer, R. Degraeve, M. Rasras, K.V. de Mieroop, P.J. Roussel, G. Groeseneken, Impact

of MOSFET gate oxide breakdown on digital circuit operation and reliability. IEEE Trans.

Electron Devices 49(3), 500–506 (2002)

3. M. Depas, T. Nigam, M.M Heyns, Soft breakdown of ultra-thin gate oxide layers. IEEE

Trans. Electron Devices 43(9), 1499–1504 (1996)

4. K. Okada, Extended time dependent dielectric breakdown model based on anomalous gate

area dependence of lifetime in ultra think silicon dioxides. Japan. J. Appl. Phys. 36(3B),

1443–1447 (1997)

5. A. Popa, An injection level dependent theory of the MOS transistor in saturation. IEEE

Trans. Electron Devices 19(6), 774–781 (1972)

6. P.E. Cottrell, R.R. Troutman, T.H. Ning, Hot-electron emission in n-channel IGFET’s. IEEE

Trans. Electron Devices 26(4), 520–533 (1979)

7. C. Hu, Lucky-electron model of channel hot electron emission. IEDM Tech. Dig. 25, 22–25

(1979)

8. S. Mahapatra, C. Parikh, V. Rao, C.R. Viswanathan, J. Vasi, Device scaling effects on

hot-carrier induced interface and oxide-trapped charge distributions in MOSFET’s. IEEE

Trans. Electron Device 47(4), 789–796 (2000)

9. J.H. Stathis, S. Zafar, The negative bias temperature instability in MOS devices. Rev.

Microelectron. Reliab. 46(2–4), 270–286 (2006)

10. S.E. Rauch, Review and reexamination of reliability effects related to NBTI-induced

statistical variations. IEEE Trans. Device Mater. Reliab. 7(4), 524–529 (2007)

11. T. Grasser, B. Kaczer, W. Goes, An energy-level perspective of bias temperature instability,

in Proceedings of International Reliability Physics Symposium (IRPS) (April 2008), pp. 28–

38

12. P.B. Ghate, Electromigration-induced failures in VLSI interconnects, in Annual Reliability

Physics Symposium (IEEE, 1982), pp. 292–299

13. D. Pierce, P. Brusius, Reliability physics of advanced electron devices electromigration.

Rev. Microelectron. Reliab. 37(7), 1053–1072 (1997)

14. J.R. Black, Electromigration failure modes in aluminum metallization for semiconductor

devices. Proc. IEEE 57(9), 1587–1594 (1969)

15. J. Yue, W. Funsten, R. Taylor, Stress induced voids in aluminum interconnects during IC

processing, in Annual Reliability Physics Symposium (IEEE, 1985), pp. 126–137

16. T.H. Kim, R. Persaud, C.H. Kim, Silicon odometer: an on-chip reliability monitor for

measuring frequency degradation of digital circuits. IEEE J. Solid-State Circ. 43(4), 874–

880 (2008)

17. T. Sato, T. Kozaki, T. Uezono, H. Tsutsui, H. Ochi, A device array for efficient

bias-temperature instability measurements, in Proceedings of European Solid-State Device

Research Conference (ESSDERC) (2011), pp. 143–146

18. H. Awano, M. Hiromoto, T. Sato, BTIarray: a time-overlapping transistor array for efficient

statistical characterization of bias temperature instability. IEEE Trans. Device Mater. Reliab.

14(3), 833–843 (2014)

19. J.B. Velamala, K.B. Sutaria, T. Sato, Y. Cao, Physics matters: statistical aging prediction

under trapping/detrapping, in Proceedings of ACM/IEEE Design Automation Conference

(DAC) (June 2012), pp. 139–144

20. P. Singh, E. Karl, D. Sylvester, D. Blaauw, Dynamic NBTI management using a 45 nm

multi-degradation sensor, in IEEE Custom Integrated Circuits Conference (Sept 2010),

pp. 1–4



240



T. Sato et al.



21. P.F. Lu, K.A. Jenkins, A built-in BTI monitor for long-term data collection in IBM

microprocessors, in Proceedings of International Reliability Physics Symposium (IRPS) (Apr

2013), pp. 4A.1.1–4A.1.6

22. H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye, Adaptive performance compensation

with in-situ timing error predictive sensors for subthreshold circuits. IEEE Trans. Very Large

Scale Integr. VLSI Syst. 20(2), 333–343 (2012)

23. S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, T. Onoye, Stochastic error rate estimation

for adaptive speed control with field delay testing, in IEEE International Conference on

Computer Aided Design (Nov 2013), pp. 107–114

24. F. Masuoka et al., A new flash E2PROM cell using triple polysilicon technology, in IEEE

International Electron Devices Meeting (IEDM) (1984), pp. 465–467

25. F. Masuoka et al., New ultra high density EPROM and flash EEPROM with NAND

structure cell, in IEEE International Electron Devices Meeting (IEDM) (1987), pp. 552–555

26. F. Masuoka, Great encounters leading me to the inventions of flash memories and

surrounding gate transistor technology. IEEE Solid-State Circ. Mag. 10–20 (2013)

27. S. Aritome, NAND flash innovations. IEEE Solid-State Circ. Mag. 21–29 (2013)

28. M. Bauer et al., A multilevel-cell 32 Mb flash memory, in IEEE International Solid-State

Circuits Conference (ISSCC) (1995), 132–133

29. K. Takeuchi et al., A 56 nm CMOS 99 mm2 8 Gb Multi-level NAND flash memory with

10 MB/s program throughput, in IEEE International Solid-State Circuits Conference

(ISSCC) (2006), pp. 144–145

30. R. Cernea et al., A 34 MB/s-program-throughput 16 Gb MLC NAND with all-bitline

architecture in 56 nm, in IEEE International Solid-State Circuits Conference (ISSCC)

(2008), pp. 420–421

31. R. Zeng et al., A 172 mm2 32 Gb MLC NAND flash memory in 34 nm CMOS, in IEEE

International Solid-State Circuits Conference (ISSCC) (2009), pp. 236–237

32. H. Kim et al., A 159 mm2 32 nm 32 Gb MLC NAND-flash memory with 200 MB/s

asynchronous DDR interface, in IEEE International Solid-State Circuits Conference

(ISSCC) (2010), pp. 442–443

33. C. Lee et al., A 32 Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes

in 32 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2010),

pp. 446–447

34. K. Fukuda et al., A 151 mm2 64 Gb MLC NAND flash memory in 24 nm CMOS

technology, in IEEE International Solid-State Circuits Conference (ISSCC) (2011), pp. 198–

199

35. T.-Y. Kim et al., A 32 Gb MLC NAND flash memory with Vth margin-expanding schemes

in 26 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2011),

pp. 202–203

36. N. Shibata et al., A 19 nm 112.8 mm2 64 Gb multi-level flash memory with 400 Mb/s/pin

1.8 V toggle mode interface, in IEEE International Solid-State Circuits Conference (ISSCC)

(2012), pp. 422–423

37. M. Helm et al., A 128 Gb MLC NAND-flash device using 16 nm planar cell, in IEEE

International Solid-State Circuits Conference (ISSCC) (2014), pp. 326–327

38. S. Choi et al., A 93.4 mm2 64 Gb MLC NAND-flash memory with 16 nm CMOS

technology, in IEEE International Solid-State Circuits Conference (ISSCC) (2014), pp. 328–

329

39. Y. Li et al., A 16 Gb 3b/cell NAND flash memory in 56 nm with 8 MB/s write rate, in IEEE

International Solid-State Circuits Conference (ISSCC) (2008), pp. 506–507

40. S.-H. Chang et al., A 48 nm 32 Gb 8-Level NAND flash memory with 5.5 MB/s program

throughput, in IEEE International Solid-State Circuits Conference (ISSCC) (2009), pp. 240–

241

41. G.G. Marotta et al., A 3 bit/cell 322 Gb NAND flash memory at 34 nm with 6 MB/s

program throughput and with dynamic 2 bit/cell blocks configuration mode for a program



6 Time-Dependent Degradation in Device Characteristics …



42.



43.

44.



45.

46.



47.

48.



49.

50.



51.



52.

53.

54.

55.

56.



57.



58.

59.

60.



61.

62.



63.



241



throughput increase up to 13 MB/s, in IEEE International Solid-State Circuits Conference

(ISSCC) (2010), pp. 444–445

Y. Li et al., 128 Gb 3 bit/cell NAND flash memory in 19 nm technology with 18 MB/s write

rate and 400 Mb/s toggle mode, in IEEE International Solid-State Circuits Conference

(ISSCC) (2012), pp. 436–437

G. Naso et al., A 128 Gb 3b/cell NAND flash design using 20 nm planar-cell technology, in

IEEE International Solid-State Circuits Conference (ISSCC) (2013), pp. 218–219

K. Kanda et al., A 120 mm2 16 Gb 4-MLC NAND flash memory with 43 nm CMOS

technology, in IEEE International Solid-State Circuits Conference (ISSCC) (2008), pp. 430–

431

C. Trinh et al., A 5.6 MB/s 64 Gb 4b/cell NAND flash memory in 43 nm CMOS, in IEEE

International Solid-State Circuits Conference (ISSCC) (2009), pp. 246–247

D. Nobunaga et al., A 50 nm 8 Gb NAND flash memory with 100 MB/s program

throughput and 200 MB/s DDR interface, in IEEE International Solid-State Circuits

Conference (ISSCC) (2008), pp. 426–427

http://www.itrs.net/home.html

K.-T. Park et al., Three-dimensional 128 Gb MLC vertical NAND flash-memory with

24-WL stacked layers and 50 MB/s high-speed programming, in IEEE International

Solid-State Circuits Conference (ISSCC) (2014), pp. 334–335

K. Takeuchi et al., A multipage cell architecture for high-speed programming multilevel

NAND flash memories. IEEE J. Solid-State Circ. 33(8), 85–96 (2012)

K.-D. Suh et al., A 3.3 V 32 Mb NAND flash memory with incremental step pulse

programming scheme, in IEEE International Solid-State Circuits Conference (ISSCC)

(1995), pp. 128–129

J.-D. Lee et al., Degradation of tunnel oxide by FN current stress and its effects on data

retention characteristics of 90-nm NAND flash memory cells, in IEEE International

Reliability Physics Symposium (IRPS) (2003), pp. 497–501

K. Prall, Scaling non-volatile memory below 30 nm, in IEEE Non-Volatile Semiconductor

Memory Workshop (NVSMW) (2007), pp. 5–10

S.W. Park, Prospect for new memory technology. Flash Mem. Summit (2012)

J.-D. Lee et al., Effects of floating-gate interference on nand flash memory cell operation.

IEEE Electron Device Lett. 23(5), 264–266 (2002)

M. Park et al., Direct field effect of neighboring cell transistor on cell-to-cell interference of

NAND flash cell arrays. IEEE Electron Device Lett. 30(2), 174–177 (2009)

J.-D. Lee et al., A new programming disturbance phenomenon in NAND flash memory by

source/drain hot-electrons generated by GIDL current, in IEEE Non-Volatile Semiconductor

Memory Workshop (NVSMW) (2006), pp. 31–33

S. Aritome et al., Novel negative Vt shift phenomenon of program-inhibit cell in 2X-3X-nm

self-aligned STI NAND flash memory. IEEE Trans. Electron Devices 59(11), 2950–2955

(2012)

Y.S. Kim et al., New scaling limitation of the floating gate cell in NAND flash memory, in

IEEE International Reliability Physics Symposium (IRPS) (2010), pp. 599–603

K. Prall, K. Parat, 25 nm 64 Gb MLC NAND technology and scaling challenges, in IEEE

International Electron Devices Meeting (IEDM) (2010), pp. 102–105

K.-T. Park et al., A zeroing cell-to-cell interference page architecture with temporary LSB

storing and parallel MSB program scheme for MLC NAND flash memories.

IEEE J. Solid-State Circ. 43(4), 919–928 (2008)

N. Mielke et al., Bit error rate in NAND flash memories, in IEEE International Reliability

Physics Symposium (IRPS) (2008), pp. 9–19

E. Yaakobi et al., Error characterization and coding schemes for flash memories, in IEEE

Global Communications Conference, Exhibition & Industry Forum (GLOBECOM) (2010),

pp. 1856–1860

R. Motwani et al., Low density parity check (LDPC) codes and the need for stronger ECC.

Flash Mem. Summit (2011)



242



T. Sato et al.



64. H. Parizi, Flash reliablity, beyond data management and ECC. Flash Mem. Summit (2013)

65. S. Tanakamaru et al., Error-prediction LDPC and error-recovery schemes for highly reliable

solid-state drives (SSDs). IEEE J. Solid-State Circ. 48(11), 2920–2933 (2013)

66. G. Dong et al., On the Use of soft-decision error-correction codes in NAND flash memory.

IEEE Trans. Circ. Syst. I 58(2), 429–439 (2011)

67. D.A. Patterson et al., A case for redundant arrays of inexpensive disks (RAID), in ACM

Special Interest Group on Management of Data (SIGMOD) (1988), pp. 108–116

68. M. Blaum et al., EVENODD: an efficient scheme for tolerating double disk failures in RAID

architectures. IEEE Trans. Comput. 44(2), 192–202 (1995)

69. M. Balakrishnan et al., Differential RAID: rethinking RAID for SSD reliability, in European

Conference on Computer Systems (2010)

70. D.-H. Lee, W. Sung, Least squares based cell-to-cell interference cancelation technique for

multi-level cell NAND flash memory, in IEEE International Conference on Acoustics,

Speech, and Signal Processing (ICASSP) (2012), pp. 1601–1604

71. R. Motwani, Architecture customized constrained coding for mitigating FGFG coupling in

flash. Flash Mem. Summit (2011)

72. S. Tanakamaru et al., Highly reliable and low power SSD using asymmetric coding and

stripe bitline-pattern elimination programming. IEEE J. Solid-State Circ. 47(1), 85–96

(2012)

73. International Technology Roadmap for Semiconductors (2013), http://www.itrs.net/

74. W. Wang et al., Compact modeling and simulation of circuit reliability for 65-nm CMOS

technology. IEEE Trans. Device Mater. Reliab. 7(4), 509–517 (2007)

75. International Electrotechnical Commission, IEC61508, Functional safety of electrical/

electronic/ programmable electronic safety-related systems, Ed.2.0 (2010-4), http://www.iec.

ch/functionalsafety/

76. ISO26262 Road vehicles -Functional safety-, First Edition, 2011-11

77. N. Kanekawa et al., Dependability in Electronic Systems (Springer, 2010). ISBN

978-1-4419-6714-5

78. Y. Sato et al., DART: dependable VLSI test architecture and its implementation. in

Proceedings International Test Conference, paper 15.2 (2012)

79. Y. Miura et al., On-chip temperature and voltage measurement for field testing, in

Proceedings of European Test Symposium (2012), p. 204

80. R. Franch, P. Restle, N. James, W. Huott, J. Friedrich, R. Dixon, S. Weitzel, K.V. Goor, G.

Salem, On-chip timing uncertainty measurement on IBM microprocessors, in Proceedings of

International Test Conference (2007), pp. 1.1.1–1.1.7

81. M.-C. Tsai, C.-H. Cheng, C.-M. Yang, An all-digital high-precision built-in delay time

measurement circuit, in Proceedings of IEEE VLSI Test Symposium (2008), pp. 249–254

82. R. Tayade, J.A. Abraham, On-chip programmable capture for accurate path delay test and

characterization, in Proceedings of International Test Conference (2008), pp. 6.2.1–6.2.10

83. X. Wang, M. Techranipoor, R. Datta, A novel architecture for on-chip path delay

measurement, in Proceedings of International Test Conference (2009), pp. 12.1.1–12.1.10

84. X. Wang, M. Tehranipoor, R. Datta, Path-RO: a novel on-chip critical path delay

measurement under process variations, in Proceedings of International Conference on

Computer-Aided Design (Nov 2008), pp. 640–646

85. M. Nicolaidis, Y. Zorian, On-line testing for VLSI-A compendium of approaches.

J. Electron. Test. Theory and Applications 12(1–2), 7–20 (1998)

86. H. Al-Asaad et al., Online BIST for Embedded Systems. IEEE Des. Test Comput. 15(4), 17–

24 (1998)

87. J. Qian et al., Logic BIST architecture for system-level test and diagnosis, in Proceedings of

Asian Test Symposium (2009), pp. 21–28

88. Y. Li, S. Makar, S. Mitra, CASP: concurrent autonomous chip self-test using stored test

patterns, in Proceedings of Design Automation and Test in Europe (2008), pp. 885–89

89. H. Inoue et al., VAST: virtualization-assisted concurrent autonomous self-test, in

Proceedings of International Test Conference, paper 12.3 (2008)



6 Time-Dependent Degradation in Device Characteristics …



243



90. Y. Sato et al., A stochastic model for NBTI-induced LSI degradation in field, in IEEE Asian

Test Symposium (2013), pp. 183–188

91. D. Ernst, N.S. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, T.

Mudge, K. Flautner, Razor: a low-power pipeline based on circuit-level timing speculation,

in Proceedings of International Symposium on Microarchitecture (Dec 2003), pp. 7–18

92. T. Sato, Y. Kunitake, A simple flip-flop circuit for typical-case designs for DFM, in

Proceedings of International Symposium on Quality Electronic Design (Mar 2007), pp. 539–

544

93. Y. Sato et al., Reduction of NBTI-induced degradation on ring oscillators in FPGA, in

Proceedings of 20th Pacific Rim International Symposium on Dependable Computing

(2014), pp. 59–67

94. K. Itoh, Adaptive circuits for the 0.5-V nanoscale CMOS era, in IEEE International

Solid-State Circuits Conference (Feb 2009), pp. 14–20

95. S. Borkar, T. Karnik, V. De, Design and reliability, in Proceedings of Design Automation

Conference (June 2004), p. 75

96. C. Wilkerson, H. Gao, A.R. Alameldeen, Z. Chishti, M. Khellah, S.-L. Lu, Trading off cache

capacity for reliability to enable low voltage operation, in Proceedings of International

Symposium on Computer Architecture (June 2008), pp. 203–214

97. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, M. Yoshimoto, A 7T/14T

dependable SRAM and its array structure to avoid half selection, in Proceedings of

International Conference on VLSI Design (Jan 2009), pp. 295–300

98. E. Seevinick, F.J. List, J. Lohstroh, Static-noise margin analysis of MOS SRAM cells.

IEEE J. Solid-State Circ. 22(5), 748–754 (1987)

99. E. Grossar, M. Stucchi, K. Maex, W. Dehaene, Statically aware SRAM memory array

design, in Proceedings of International Symposium on Quality Electronic Design (Mar

2006), pp. 6–30

100. N. Binkert, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, D.A. Wood, B.

Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, T.

Krishna, The gem5 simulator. ACM SIGARCH Comput. Archit. News 39(2), 1–7 (2011)

101. Standard Performance Evaluation Corporation, The SPEC CPU 2006 Benchmark Suite.

http://www.specbench.org

102. J. Yao, S. Okada, H. Shimada, K. Kobayashi, Y. Nakashima, DARA: a low-cost reliable

architecture based on unhardened devices and its case study of radiation stress test, in

NSREC’12 (July 2012)



Chapter 7



Connectivity in Wireless

Telecommunications

Kazuo Tsubouchi, Fumiyuki Adachi, Suguru Kameda,

Mizuki Motoyoshi, Akinori Taira, Noriharu Suematsu,

Tadashi Takagi, Hiroshi Oguma, Minoru Fujishima, Ryuji Inagaki,

Masaomi Tsuru, Eiji Taniguchi, Hiroshi Fukumoto,

Akira Matsuzawa, Masaya Miyahara, Makoto Iwata,

Fumihiro Yamagata and Noboru Izuka



Abstract Good connection quality is a most important requirement in telecommunication systems. For the public wireless network, however, primary attention

has so far been paid to providing broader bandwidth for rapidly expanding subscriber base. In this chapter, the connectivity of wireless telecommunication is

undertaken as a central issue, while keeping in mind that the next-generation

wireless will take on broader and ubiquitous machine-to-machine (M2M)

K. Tsubouchi (✉) ⋅ F. Adachi ⋅ S. Kameda ⋅ M. Motoyoshi ⋅ A. Taira

N. Suematsu ⋅ T. Takagi

Tohoku University, Sendai, Japan

e-mail: tsubo@riec.tohoku.ac.jp

F. Adachi

e-mail: adachi@ecei.tohoku.ac.jp

S. Kameda

e-mail: kameda@riec.tohoku.ac.jp

M. Motoyoshi

e-mail: mizuki@riec.tohoku.ac.jp

N. Suematsu

e-mail: suematsu@riec.tohoku.ac.jp

T. Takagi

e-mail: t-takagi@riec.tohoku.ac.jp

H. Oguma

National Institute of Technology, Toyama College, Toyama, Japan

e-mail: oguma@nc-toyama.ac.jp

M. Fujishima

Hiroshima University, Higashihiroshima, Japan

e-mail: fuji@hiroshima-u.ac.jp

R. Inagaki ⋅ M. Tsuru ⋅ E. Taniguchi ⋅ H. Fukumoto

Mitsubishi Electric Corporation, Kamakura, Japan

© Springer Japan KK, part of Springer Nature 2019

S. Asai (ed.), VLSI Design and Test for Systems Dependability,

https://doi.org/10.1007/978-4-431-56594-9_7



245



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