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6 Appendix to Chapter 2: The Case of a Scientific Instrument System—An Example Electronic System

6 Appendix to Chapter 2: The Case of a Scientific Instrument System—An Example Electronic System

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2 Design and Development of Electronic Systems for Quality and Dependability

PC (Microsoft OS)

Measurement control and analysis


Diffraction data

Measurement Control

Embedded computer

Microprocessor SH-2A

Stage and data acquisition controller Cyclone 1

High Voltage Controller Cortex M3

Measurement chamber

(X-ray shields)


X-ray source



Failsafe shutdown signal

Chamber door sensor

X-ray diffraction image



Sample stage

Diffracted X-rays

Fig. 2.12 A simplified schematic of an X-Ray diffractometer. The X-ray image that results from

the physical phenomenon called “diffraction” of the incident X-rays contains the signature of

microscopic structure and composition of substances the sample consists of

structure of the sample. (It is to be noted here that in most embedded systems the

PC, on which the embedded software is developed and compiled, is detached from

the embedded system at this point in time. The embedded system runs on its own

except during the upgrading of software or servicing for maintenance.) The SH-2A

running on the iTRON real-time operating system switches over a few different

tasks on the priority basis accepting interrupt requests from the instrumentation

hardware, including the X-ray source, sample stage, and detector, and reports the

measurement result to the PC. The SH-2A, having a multiple interrupt controller

with 16 interrupt ports, is convenient for use in a hard real-time environment such

as the X-ray diffraction measurement, in which the gating for the detector has to be

precisely synchronized with the motion of the 3-D sample stage within less than

0.1 ms. Tasks are dispatched through the fast 50 MHz data bus to the

Cyclone FPGA. The SH-2A can take care of instructions that can take time longer

than 10 ms to respond to through its various I/O ports such as UART and SPI. The

rationale for the choice of an SH-2A as the processor for this system is the capacity

and the speed (>100 MHz) to run the real-time iTRON OS and the sufficient I/O

capabilities. Figure 2.14 shows photographs of printed circuit boards for an X-ray

diffractometer. The motherboard (a) contains a microprocessor SH-2A 7201 from

Renesas that runs the iTRON real-time operating system, an FPGA Cyclone-1 from


S. Asai

General-purpose PC

User’s purpose

Analysis of


data to obtain

the atomic

structure of

the sample

as industrial


Measurement control

(Control program written in

C++ or C# has been

compiled/assembled and

downloaded to the

embedded flash memory)

Data analysis



So ware

Embedded computer


Cortex M3






Stage and data

acquisi on control





X-ray source

Diffrac on





Instrumenta on





Flash memory

D-to-A converter

and driver

A-to-D converter

and signal readout




Fig. 2.13 A simplified block diagram of an X-ray diffractometer. User’s purpose is to have the

intended measurement done automatically and analyze its results as he/she pleases. The embedded

system automates the instrumentation using the source, optics, movable stages, etc. The

general-purpose computer is used to give macroscopic commands for the embedded computer to

execute the measurement and collect data, and then to analyze the data by using the software of

his/her liking. Medical imaging and simple robotic systems have a similar structure

Fig. 2.14 Photographs of an embedded computer system for a scientific instrument called X-ray

diffractometer. The motherboard (a) contains a microprocessor SH-2A from Renesas that runs the

iTRON real-time operating system, an FPGA from Altera, and memory chips. The daughterboard

(b) is for motor-control contains four safety relays (bottom right) mandated by the regulation to

prevent inadvertent exposure to the X-rays (health hazard). Pictures courtesy of Rigaku


2 Design and Development of Electronic Systems for Quality and Dependability


Altera, 14 MB flash NOR memory chip from Spansion, two 32 MB SDRAM chips.

The daughterboard (b) contains an ARM Cortex M3 microprocessor from ST

Microsystems and four safety relay mechanisms as major components, and is used

for the following two purposes; one is controlling the X-ray generator including the

vacuum tube, high-voltage power supply, cooling waters, etc., and the other is

preventing inadvertent X-ray exposure from happening. The latter may thus be

called a functional safety feature of the system. Other safety mechanisms are

installed to comply with CE marking directives (low-voltage, electromagnetic and



1. Project Management Institute, “What is Project Management?” http://www.pmi.org/, https://


2. Microsoft Store URL: “Microsoft Project,” https://www.microsoftstore.com/store/msusa/en_


3. D. Patterson, J. Hennessy, Computer organization and design, the hardware/software

interface, ARM edn. (U.S.A, Morgan Kauffman, Cambridge, 2016)

4. Refer to EDA (Electronic Design Automation) tool vendor websites, for example: Synopsis,

Cadence, Mentor Graphics, for example

5. SPICE, A circuit simulator that originates at the University of California at Berkeley and has

disseminated by firms specializing in design tools. Tools are available from vendors [4]

6. Refer to the websites of Mathworks, for example, for ‘model-based’ design tools: https://


7. Refer to the websites of ‘multi-physics’ simulator vendors, ANSYS, COMSOL, for example:

http://www.ansys.com/products/multiphysics https://www.comsol.jp/multiphysics

8. Wikipedia, “Bill of Materials,” https://en.wikipedia.org/wiki/Bill_of_materials

9. There is abundant information available on the internet net about this topic. Please throw key

words such as “manufacturing bom” at a search engine. Most are offered commercially

10. ISO Website, “Standards Catalogue, ISO/IEC JTC 1/SC 7- Software and systems

engineering” http://www.iso.org/iso/iso_catalogue/catalogue_tc/catalogue_tc_browse.htm?


11. FDA, “General Principles of Software Validation; Final Guidance for Industry and FDA

Staff,” FDA website: http://www.fda.gov/RegulatoryInformation/Guidances/ucm085281.htm

12. FDA, “Software As a Medical Device (SAMD): Clinical Evaluation, FDA Website”;



13. International Standards, IEC/ISO 31010, “Risk management -Risk assessment techniques,”


14. For example, Dr. Michael Stamatelatos, “Probabilistic Risk Assessment: What is it and Why

is it worth performing?” http://www.hq.nasa.gov/office/codeq/qnews/pra.pdf. The internet

provides rich reference to PRA which is worth for anyone who is interested in building

dependability in electronic products to take time going over. A lot of consultancy firms offer

help in risk analysis as well. FDA

15. International Standards, ISO 11231:2010, “Space Systems—Probabilistic risk assessment—




16. International Standard, IEC 61508, “Functional safety of electrical/electronic/programmable

electronic safety-related systems,” http://www.iec.ch/functionalsafety/


S. Asai

17. International Standard, IEC 61508-5 “Functional safety of electrical/electronic/programmable

electronic safety-related systems—Part 5: Examples of methods for the determination of

safety integrity levels,” https://webstore.iec.ch/publication/5519

18. International Standard, ISO 26262, Road-vehicles—Functional safety,”

19. T. Grossman, J.L. Livingstone, The portable MBA in finance and accounting, 4th edn, Wiley,

New York, Sept 2009; see also: R.C. Higgins, Analysis for Financial Management, 10th ed.,

McGraw-Hill Education, December, 2011 for return-on-investment performance indexes

similar but with different definitions

20. Refer to the Intel product support website at the following. http://www.intel.com/content/


21. E. Ibe et al., Radiation-Induced Soft Errors, Section 3.1 of this book

22. H. Kawaguchi, Soft-Error Tolerant SRAM Cell Layout, Section 3.2 of this book

23. K. Kobayashi, Radiation-Hard Flip-Flops, Section 3.3 of this book

24. Y. Mitsuyama, Soft-Error-Tolerant Reconfigurable Architecture, Section 3.4 of this book

25. M. Sugihara, Simulation and Design Techniques for Memory Systems, Section 3.5 of this


26. M. Nagata et al., “Electromagnetic Compatibility of CMOS ICs,” Section 4.1 of this book

27. M. Nagata, “Electromagnetic Noise Immunity in Memory Circuits,” Section 4.2 of this book

28. M. Nagata, “Power Noise of IC Chips in Assembly and Its Mitigations,” Section 4.3 of this


29. N. Yamasaki, “Responsive Link for Noise-tolerant Real-time Communications,” Section 4.4

of this book

30. H. Onodera, “Overview of Device Variations,” Section 5.1 of this book

31. H. Onodera, “Monitoring and Compensation for Variations in Device Characteristics,”

Section 5.2 of this book

32. Y. Miura et al., “Highly Accurate Delay-Time Measurement by an On-Chip Circuit,”

Section 5.3 of this book

33. T. Sato et al., “Timing-Error-Sensitive Flip-Flop for Error-Prediction,” Section 5.4 of this


34. K. Nii et al., “Fine-Grain Assist Bias Control for Dependable SRAM,” Section 5.5 of this

book Discussed in this chapter are general review of the topic (Sections 5.1 and 5.2), on-chip

delay-time measurement (Section 5.3), timing-error-sensitive flip-flop for error prediction

(Section 5.4) and fine-grained voltage assist for SRAM that works against variations

(Section 5.5)

35. T. Sato et al., “Time-Dependent Degradation in Device Characteristic,” Section 6.1 of this


36. S. Tanakamaru et al., “Degradation of Flash Memories and Signal Processing for

Dependability,” Section 6.2 of this book

37. Y. Sato et al., “In-Field Monitoring of Device Degradation for Predictive Maintenance,”

Section 6.3 of this book

38. M. Yoshimoto et al., “A Reconfigurable SRAM Cache Design for Wide-Range Reliable

Low-Voltage Operation,” Section 6.4 of this book

39. H. Shimada et al., “Runtime Self Reconstruction for Soft/Hard Fault Toleration,” Section 6.5

of this book

40. G. Moor, Cramming More Components onto Integrated Circuits. Electron. Mag. 19, 4 (1965)

41. For actual trend in the speed of integration, refer, for example, to: Intel Website, “50 years of

Moore’s Law,” http://www.intel.com/content/www/us/en/silicon-innovations/moores-lawtechnology.html

42. B. David, Understanding Moore’s Law, Four Decades of Innovation, Chapter 4 The Future of

Integration, p. 39, CHF Publications, Philadelphia (2006)

43. M. Koyanagi et al., “Connectivity Issues in 3D Packaging,” Section 8.3 of this book

44. M. Koyanagi et al., “A 3-D VLSI Architecture for Future Automotive Visual Recognition,”

Chapter 26 of this book

2 Design and Development of Electronic Systems for Quality and Dependability


45. On-chip error correction in DRAM from Intelligent Memory is said to be capable of

correcting single-bit errors on the fly, “ECC DRAM,” http://www.intelligentmemory.com/


46. S. Tanakamaru, “Design and Application of Dependable Non-Volatile Memory Systems,”

Chapter 18 of this book

47. M. Yoshimoto, “Design of SRAM Resilient against Dynamic Voltage Variations,” Chapter

17 of this book

48. M. Yoshimoto, “A Low-Latency DMR Architecture with Efficient Recovery Scheme Exploiting Simultaneously Copiable SRAM,” Chapter 25 of this book

49. Refer, for example, to; Wikipedia, “Dual Modular Redundancy,” https://en.wikipedia.org/


50. Refer, for example, to; Wikipedia, “Triple Modular Redundancy,” https://en.wikipedia.org/


51. T. Kuroda et al., “Connectivity in Electronic Packaging,” Section 8.1 of this book

52. T. Kuroda et al., “Wireless Interconnect in Electronic Systems,” Chapter 21 of this book

53. H. Ishikuro et al., “Connectivity in Electronic Packaging,” Section 8.2 of this book

54. H. Ishikuro et al., “Wireless Power Delivery Resilient against Loading Variations,” Chapter

22 of this book

55. T. Yoneda et al., “Asynchronous Network on Chip,” Section 9.3 of this book

56. T. Yoneda et al., “Dependable Network-on-Chip Platform for Safety-Critical Automotive

Applications,” Chapter 19 of this book

57. M. Imai et al., “Fault Detection and Reconfiguration in NoC-Coupled Multiple CPU Cores for

Deadline-Specified Periodical Tasks,” Section 12.5 of this book

58. K. Kise, “An On-Chip Router Architecture for Multicore Processor,” Chapter 20 of this book

59. Y. Nakabo, “Responsiveness for Hard-Real Time Control,” Section 9.1 of this book

60. N. Yamasaki et al, “Microprocessor Architecture for Real-Time Processing,” Section 9.2 of

this book

61. N. Yamasaki et al, “Responsive Multithreaded Microprocessor for Hard-Real Time Robotic

Applications,” Chapter 24 of this book

62. H. Hihara et al., “A Re-Configurable Processor Architecture for Space Applications,” Chapter

27 of this book

63. T. Fujino et al., “The tamper resistance against Malicious Attacks on Security VLSIs,”

Section 10.1 of this book

64. Y. Hori, “Methods for Tampering Cryptographic VLSIs,” Section 10.2 of this book

65. M. Shiozaki, “Tamper-Resistant Symmetric-Key Cryptographic Circuits,” Section 10.3 of

this book

66. M. Yoshikawa et al., “Verification Methods for Tamper-Resistant VLSI Design,” Chapter

10.4 of this book

67. K. Nii et al., “A SRAM-Based Physically Unclonable Function for Authentication and

Encryption,” Chapter 29 of this book

68. M. Yoshimura, “A Method for Evaluating Vulnerability to Scan-Based Attacks,” Section 10.6 of this book

69. Y. Hori, “Evaluation of Tamper Resistance of VLSI, “Section 10.7 of this book

70. D. Suzuki, “Security Components for Systems-Level Authentication,” Chapter 28 of this


71. F. Adachi et al., “Challenges for Dependable Public Wireless Telecommunications,”

Section 7.1 of this book

72. K. Tsubouchi et al., “Challenges for Dependable Air,” Section 7.2 of this book

73. T. Takagi, “Challenges in Wireless Signal Processing,” Section 7.3 of this book

74. M. Fujishima, “Broad-Band RF Circuit for Versatile, Dependable Wireless Telecommunications,” Section 7.4 of this book

75. R. Inagaki et al., “All-Si CMOS Front-End ICs for Multi-Band Micro-/Millimeter-Wave

Communications,” Section 7.5 of this book

76. A. Matsuzawa et al., “Dependable Analog-to-Digital Converter,” Section 7.6 of this book


S. Asai

77. K. Tsubouchci, “Multimode Frequency-Domain Equalizer for Heterogeneous Wireless

System,” Section 7.7 of this book

78. S. Kameda, “Network Technology for Heterogeneous Wireless System,” Section 7.8 of this


79. K. Tsubouchi et al., “Connectivity in Wireless Communications,” Chapter 23 of this book

80. S. Kameda, “Timing Dependability for Wireless Network,” Section 9.4 of this book

81. N. Kanekawa, “Historical Review of Faults and Unidentified Future Threats,” Section 12.1 of

this book

82. T. Miyoshi, “Challenges to Dependability at Data Centers,” Section 12.2 of this book

83. M. Fujita et al., “Post-Silicon Validation and Patchable Hardware for Rectification,”

Section 12.3 of this book

84. S. Kajihara et al., “Logging and Using Field-Test Data for Improved Dependability,”

Section 12.4 of this book

85. H. Takizawa et al., “Checkpoint-Restart in Heterogeneous Multiple-Processor Systems,”

Section 12.6 of this book

86. K. Takayama at al., “Verification and Test Coverage,” Section 11.1 of this book

87. M. Fujita et al., “Design Errors and Formal Verification,” Section 11.2 of this book

88. M. Fujita, “Formal Verification and Debugging of VLSI Logic Design for Systems

Dependability: Experiments and their Evaluation,” Chapter 14 of this book

89. H. Yasuura, “Design Automation for Reliability,” Chapter 13 of this book

90. S. Oho et al., “Virtualization: System-Level Fault Simulation of SRAM Errors in Automotive

Electronic Control System,” Chapter 15 of this book

91. K. Hatayama et al., “Circuit and System Mechanisms for High Field Reliability - DART

Technology,” Chapter 16 of this book

92. M. Inoue et al., “High Quality Delay Testing for In-Field Self-Test,” Section 11.3 of this book

93. T. Yoneda et al., “Temperature- and Voltage-Variation-Aware Delay Test,” Section 11.4 of

this book

94. L. Young, Telecom Experts Plot a Path to 5G, in IEEE Spectrum IEEE. http://spectrum.ieee.

org/telecom/wireless/telecom-experts-plot-a-path-to-5g. Accessed 6 Oct 2015

95. Refer to Rigaku Corporation website for information regarding X-ray diffraction and X-ray

diffractometer. http://www.rigaku.com/en

Part II

VLSI Issues in Systems Dependability

Chapter 3

Radiation-Induced Soft Errors

Eishi H. Ibe, Shusuke Yoshimoto, Masahiko Yoshimoto,

Hiroshi Kawaguchi, Kazutoshi Kobayashi, Jun Furuta,

Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye,

Hiroyuki Kanbara, Hiroyuki Ochi, Kazutoshi Wakabayashi,

Hidetoshi Onodera and Makoto Sugihara

Abstract We will begin by a quick but thorough look at the effects of faults, errors

and failures, caused by terrestrial neutrons originating from cosmic rays, on the

terrestrial electronic systems in the variety of industries. Mitigation measures, taken

at various levels of design hierarchy from physical to systems level against

neutron-induced adverse effects, are then introduced. Challenges for retaining

robustness under future technology development are also discussed. Such challenges in mitigation approaches are featured for SRAMs (Static Random Access

Memories), FFs (Flip-Flops), FPGAs (Field Programmable Gate Arrays) and

computer systems as exemplified in the following articles: (i) Layout aware

E. H. Ibe (✉)

Exapalette, LLC., Tokyo, Japan

e-mail: eishi_h_ibe@exapalette.com

S. Yoshimoto ⋅ M. Yoshimoto ⋅ H. Kawaguchi

Kobe University, Kobe, Japan

K. Kobayashi ⋅ J. Furuta

Kyoto Institute of Technology, Kyoto, Japan

Y. Mitsuyama

Kochi University of Technology, Kochi, Japan

M. Hashimoto ⋅ T. Onoye

Osaka University, Osaka, Japan

H. Kanbara

Advanced Science, Technology & Management Research Institute of KYOTO

(ASTEM), Kyoto, Japan

H. Ochi

Ritsumeikan University, Kyoto, Japan

K. Wakabayashi

NEC, Tokyo, Japan

H. Onodera

Kyoto University, Kyoto, Japan

M. Sugihara

Kyusyu University, Kyusyu, Japan

© Springer Japan KK, part of Springer Nature 2019

S. Asai (ed.), VLSI Design and Test for Systems Dependability,




E. H. Ibe et al.

neutron-induced soft-error simulation and fault tolerant design techniques are

introduced for 6T SRAMs. The PNP layout instead of conventional NPN layout is

proposed and its robustness is demonstrated by using the MONTE CARLO simulator PHITS. (ii) RHBD (Radiation-Hardened By Design) FFs hardened by using

specially designed redundant techniques are extensively evaluated. BCDMR

(Bistable Cross-Coupled Dual Modular Redundancy) FFs is proposed in order to

avoid MCU (Multi-Cell Upset) impacts on FF reliability. Its robustness is

demonstrated thorough a set of neutron irradiation tests. (iii) CGRA

(Coarse-Grained Reconfigurable Architecture) is proposed for an FPGA-chip-level

tolerance. Prototype CGRA-FPGA chips are manufactured and their robustness is

demonstrated under alpha particle/neutron irradiation tests. (iv) Simulation techniques for failures in heterogeneous computer system with memory hierarchy

consisting of a register file, an L1 cache, an L2 cache and a main memory are also

proposed in conjunction with masking effects of faults/errors.

Keywords Terrestrial neutron








Heterogeneous computer system

Register file


Mitigation measures


Fundamentals and Highlights in Radiation-Induced


Eishi H. Ibe, Exapalette, LLC


Hierarchy of Faulty Conditions of an Electronic


Reliability is gaining monumental spotlights as the foremost property that is

indispensable for the overall worth of electronic products, in particular, with respect

to radiation hardness at the ground [1–3]. Once failures take place in electronic

systems in the market, the news is spread over the world immediately though the

internet and massmedia and the products or even the vender companies may, in the

worst case, lose their business chance for a long period of time.

It is believed that the failures should have some sequential steps of symptoms to

result in failures in almost all the troubles. In the most electronic systems, the

symptom starts with a simple fault in the substrate of a circuit board in the system.

Before the fault would grow the fatal failure, there should be many kinds of

symptoms towards failures in a variety of situations. In many cases, a substantial

3 Radiation-Induced Soft Errors


Fig. 3.1 Hierarchy of faulty

conditions: fault-error-failure







part of faults may be disappeared or eliminated during propagation by a certain

logical/timing masking effects as illustrated in Fig. 3.1, but some may be captured

and fixed in memory elements such as SRAM, DRAM, flash memory, flip-flops,

and so on. Once these faults are fixed in the memory elements, they have a lot more

chance to cause the system failed.

It is important, therefore, to detect the faults, errors, and onsets of the failure, and

eliminate them at the early stage to prevent fatal failure.

In the present chapter, we will show the basic understandings and examples of

countermeasures against evolving threat of soft-error in electronic systems induced

by terrestrial neutrons in VLSI devices and systems.


Sources of Neutrons in the Field and Fundamentals

of Terrestrial Neutrons

In space applications, primary cosmic-ray (electrons, protons, and heavy ions)induced soft-errors and hard-errors (permanent errors by which the device is

mechanically destructed) are major concerns in reliability, which may cause failures

and eventually determine the life of a space craft [4].

Meanwhile, when energetic cosmic ray protons enter into the atmosphere (troposphere and stratosphere) of the Earth, some protons undergo nuclear spallation


E. H. Ibe et al.

reaction with nuclei (mainly nitrogen and oxygen nuclei) in the atmosphere to

produce a number of light particles or secondary cosmic rays including neutrinos,

photons, electrons, muons, pions, protons, and neutrons. As the cosmic rays are

deflected by Heliomagnetic field or the Sun’s activity whose intensity has about

11-year cycle, strength of neutrons at the ground has also about 11-year cycle [5].

The neutron flux at the ground is the lowest, during the solar maximum (states when

the Sun is the most active), while it is the highest at the solar minimum (states when

the Sun is the least active).

Since a secondary neutron causes a cascade of spallation reactions in the

atmosphere, it produces a shower of secondary particles and radiations that reaches

the ground of the Earth. As the thick air layer over the ground can shield neutrons,

strength (both of flux and energy) of neutrons depends upon altitude with slight

dependency on atmospheric pressure [6]. Compared to neutron flux at the avionics

altitude (about 10,000 m), therefore, the neutron flux at terrestrial altitude is much

lower by a factor of 100–300.

The cumulative flux, which is the sum of total flux from the minimum neutron

energy determined by some practical reason (in some standards like JESD89A [7]

as below, for example) to the maximum neutron energy, is summarized in Fig. 3.2

with respect to of the terrestrial neutron flux estimated at the NYC sea level [1].

Figure 3.2a can be used for evaluation of the effects of thermal (about 25 meV) or

low-energy (<1 MeV) neutrons, and Fig. 3.2b can be used for evaluation of the

effects of high-energy (>1 MeV) neutrons. The total flux beyond 10 meV can be

estimated 13 n/cm2/h from Fig. 3.2b, which is consistent with JESD89A setting [7].

It is noteworthy that the energy of terrestrial neutrons ranges widely from thermal

(25 meV) to high-energy (>1 GeV) and its total flux is about 50 n/cm2/h at the

ground including NYC sea level.

Fig. 3.2 Cumulative neutron flux at the NYC sea level. a Low-energy (<1 MeV) neutrons,

b high-energy (>1 MeV) neutrons (2015©IEEE [1])

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6 Appendix to Chapter 2: The Case of a Scientific Instrument System—An Example Electronic System

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