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1 Example of a simple analog to digital converter, the Flash ADC

# 1 Example of a simple analog to digital converter, the Flash ADC

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Analog to digital converter

89

(1,0,0), (1,1,0), (1,1,1). If the reference voltage is 1.0 V, we can then detect 3 transition

levels of input voltage, 1/4, 2/4, 3/4 V and four possible intervals (0-0.25, 0.25-0.5, 0.50.75 and >0.75) corresponding to the numbers 0-3 (Table 4.1). In the two’s complement

binary code, this corresponds to the numbers 00, 01, 10, 11. Since the data values are

contained in a 2 bit word, using the whole range available, we call this a 2 bit converter.

The number out of an ADC is commonly called counts.

In the above example, only positive voltages were digitized, but our signals also contain

negative voltages. We can get the negative signals by adding another ADC with a

negative reference voltage so one ADC would give out counts for the negative signals

and the other for the positive signals. The other alternative is to add a voltage of half the

reference voltage, to the input signal so that the voltages reaching the ADC never

become negative. The ADC now should have the output range +2 to -2 counts instead of

the 0-3 counts (when the offset of 2 has been subtracted). But this would be five states,

not four! With 2 bit representing positive and negative values, we only have the values

+2 to –1 to use (as defined in the two’s complement code). Actually, in bipolar

converters, since the binary full scale is not exactly symmetric, the offset subtracted is

not exactly half of the scale, but half a count less, to avoid this bias. Table 4.1 gives the

input and output levels for this case.

For high resolution (many bit) converters, one can simply subtract half of the full scale

without significant error.

V input

-3/8 to –1/8

-1/8 to +1/8

+1/8 to +3/8

+3/8 to +5/8

V center

-0.25

0

0.25

0.5

0.00 to 0.25

0.25 to 0.5

0.5 to 0.75

0.75 to 1

0

1

2

3

Output code

11 (-1)

00 (0)

01 (1)

10 (2)

Table 4.1 Input and output to flash ADC. First column gives the voltage in; second column, the

center voltage of each interval; third, the voltage input into the converter itself after adding (0.5 V 0.125 V) (half the full scale minus half a count); third column, the numbers out and the last column

the two’s complement code and its decimal value in parenthesis. Numbers in column 3 and 4

correspond to the example with input of only positive numbers.

Flash ADC’s are extremely fast and very expensive if a high resolution is needed since

one comparator is needed for each level, so if the signal is going to be resolved with

10000 levels, 9999 comparators and precision references are needed. Flash ADC’s are

not much used in seismology but illustrate some of the characteristics of the ADC.

We will now define some of the basic properties of ADC’s to have in mind when

continuing the description of common ADC’s :

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CHAPTER 4

Resolution. The smallest step that can be detected. In the above example, the smallest

step was 0.25 V, which is then the resolution corresponding to one change of the least

significant bit (LSB, the rightmost bit). For a high dynamic range digitizer, this could be

0.1 to 1 µV. ADC resolution is also labeled ADC sensitivity. The higher the resolution,

the smaller a number is given. As it was described in the section on sensors, the output

from a passive sensor can be in the nV range in which case many digitizers will need a

preamplifier. The number of bit is also often referred to as resolution. Most ADC’s have

an internal noise higher than one count: In this case, the number of noise-free bits,

rather than the total bit number, limits the effective resolution. For instance, one count

corresponds to 0.3µV in a 24 bit ADC with full-scale of ±2.5V, but it may have a noise

of 2µV peak-to-peak, and signals under this level may not be resolved in practice.

Gain. The sensitivity expressed in counts/V. It can be derived from resolution. If e.g.

the resolution is 10 µV, the gain would be 1count/(10-5V) = 105 counts/V.

Sample rate. Number of samples acquired per second. For seismology, the usual rates

are in the range 1 to 200 Hz (or, more specifically, samples per second – sps) while for

exploration seismology, sample rates can be more than 1000 Hz. In general, the

Maximum input or full-scale (FS). The maximum input for the ADC. Using any higher

input will result in the same output. In the example above, the maximum input is 1.0 V

or in the bipolar mode ±0.5V. Typical values are ±1 to ±30 V.

Dynamic range. Defined as the ratio between the largest and smallest value the ADC

can give. In the above example, the dynamic range = 4/1 = 4, or in dB, 20·log(4) = 12

dB. This can be a bit misleading since both negative and positive numbers are input and

the ADC has to work in bipolar mode. So the real dynamic range is only half, in this

case 6 dB. However, dynamic ranges given in dB for ADC’s are sometimes given for

the full range. For some digitizers, the lowest bits only contain noise, so the dynamic

range is defined as the ratio between the largest input voltage and the noise level of the

digitizer. This number can be substantially smaller than the theoretical largest dynamic

range of a digitizer and may depend on the data rate or sampling frequency. So, to give

one number for the dynamic range, a frequency bandwidth should ideally also be given.

Dynamic range in terms of bit. The dynamic range can also be given as number of bits

available in the output data sample. An n-bit converter then gives the numbers 0-2n or in

bipolar mode ±2n-1. In the example in Table 4.1, we have a 2-bit converter. This way of

giving the ADC dynamic range is the most common and there is no confusion about

what the meaning is. In seismology we mostly use 12, 16 and 24 bit converters. As seen

later, the 24 bit converters give out 3 bytes, but in many cases only the 17-22 more

significant bits are noise free. So, like for dynamic range, the usable dynamic range for

a 24-bit converter could be given as e.g. 18 bit.

Accuracy. The absolute accuracy is a measure of all error sources. It is defined as the

difference between the input voltage and the voltage representing the output. Ideally this

error should be ±LSB/2 and this is achieved by several low and medium-resolution

Analog to digital converter

91

commercial ADC’s (it is more difficult for higher resolution ones). The error only due

to the digitization steps (±LSB/2) is also called the quantization error.

Noise level. Number of counts out if the input is zero (subtracting DC offset). Ideally,

an ADC should give out 0 counts if the input is zero. This is usually the case for low

dynamic range digitizers 12-14 bit, but rarely the case for high dynamic range digitizers

(see section on 24 bit digitizers). The noise level is most often given as an average in

terms of RMS noise measured over many samples. A good 24-bit digitizer typically has

an RMS noise level of 2 counts.

Conversion time. The minimum time required for a complete conversion. Often it is

expressed by the maximum data rate or sampling frequency. Due to the finite time

required to complete a conversion, many converters use as input stage a sample and

hold circuit, whose function is to sample the analog signal before the start of a

conversion and hold the converter input constant until it is complete to avoid conversion

errors. This is not required with sigma-delta converters (see later), as they track the

signal continuously and their output represents an average of the input signal value

during the conversion interval.

Cross talk. If several channels are available in the same digitizer, a signal recorded with

one channel might be seen in another channel. Ideally this should not happen, but it is

always present in practice. The specification is given in dB meaning how much lower

the level is in the neighboring channel. A 24 bit digitizer might have cross talk damping

of 80 dB or a factor of 10 000 damping. If the input in channel 1 is at the maximum

giving ±223 counts out and channel 2 has no signal, the output of channel 2 caused by

cross talk would still be ±223 /10000=839 counts. This is well above the noise level for

most 24-bit digitizers, so cross talk creates a clear artificial signal in this case. In

practice, the signal shape and level is often similar in the different channels (e.g. for a 3

component station), so the problem might not be as bad as it sounds, but it certainly

should not be ignored. A good 24-bit digitizer has 120 dB of damping or better (see

Table 4.6). Cheaper multichannel digitizers use a single ADC and an analog

multiplexer, which connects different inputs sequentially to the ADC input. This limits

the cross-talk separation because analog multiplexers have limited performances. For

high resolution digitizers, one digitizer per channel is preferred.

Non-linearity. If the analog input is a linear ramp, this parameter is the relative

deviation of the converter output from the ideal value. It is expressed with relation to

full scale (FS), e.g. 0.01% of FS. For high dynamic range converters, it is important

because a poor linearity may cause two different signals at the input to be

intermodulated (the amplitude of one depends on the other) at the output. Usually it is

not a problem with modern sigma-delta converters.

Input impedance. The input impedance (ohm). Ideally it should be as high as possible in

order to have little influence on the sensor or other connected equipment. A typical

value is 1 Mohm.

Offset. If the input is zero, the offset is the DC level (the average) of the output. This

could also be called the DC shift of the ADC. There is nearly always some offset, either

CHAPTER 4

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caused by the ADC itself or caused by the components connected to the ADC. The

ADC might have a possibility of adjusting the offset by changing some reference

voltage. A small offset is of no importance, but any offset will limit the dynamic range

since the ADC will reach its maximum value (positive or negative) for smaller input

values than its nominal full-scale. Figure 4.3 shows an example where the effect of the

offset is to reduce the dynamic range by a factor of 2. The offset will be temperature

dependent, but usually this is a small problem with a drift of typically less than 1 µV/ºC.

+V

0

-V

Figure 4.3 Effect on dynamic range when a large offset is present. The range of the ADC is ±V.

The large amplitude signal (left) has no offset and amplitude is ±V. The smaller amplitude signal

(right) has an offset of V/2 and the input signal that can be recorded by the ADC is now limited to

+V/2 to –3V/2.

Now that the properties of ADC’s have been given, we can continue to describe

One of the simplest approaches of implementing an ADC is the ramp ADC. Figure 4.4

shows a simplified diagram. The control logic sends a signal to the ramp generator to

start a conversion. The ramp generator then generates a ramp signal starting from level

0 (seen on left). The ramp signal enters the comparator and once the ramp signal is

larger than or equal to the input signal, the output from the comparator switches from

zero to 1. At the same time as the ramp generator starts, the counter will start to count

the number of levels on the ramp. When the comparator switches to level 1, the control

logic will stop the counter and the number reached by the counter is then a measure of

the input voltage. After some time, the counter is reset and a new sample can be taken.

A cheaper variant of this type of digitizer generates a ramp by integrating a reference

voltage while a clock signal drives a counter. When the ramp voltage reaches the input

voltage, the digitizer just reads the time elapsed as the counter output. The counter and

integrator are then reset for a new conversion.

Analog to digital converter

93

Comparator

-

Stop Counting

+

Ramp

generator

Start-stop

generator

Control

logic

Clock input

Start-stop

counter

Counter

Digital output

Figure 4.4 Ramp ADC, see text.

The Ramp ADC is relatively slow and even slower if a high resolution is required. It

also becomes slower as the number increase in size since the counter has to count longer

for large amplitudes. An improvement of the ramp ADC is the successive

approximation ADC, which is almost identical to the ramp ADC except that it has a

more sophisticated control circuit. The converter does not test all levels, but first tests if

the input level is below or above half the full scale, thus the possible range has been

halved. It then tests if the input level is above or below the middle of this new range etc.

The conversion time is much smaller than for the ramp ADC and constant. This design

is the most popular of the classical type of ADC’s. A typical 16 bit digitizer of this type

may have a conversion time of 20µs, which is fast enough for multichannel seismic data

acquisition. Nevertheless, it requires a sample and hold circuit.

We have all used a digital multimeter. It contains a digitizer sampling a few times a

second which can be seen by how often the numbers change on the display. Most

multimeters have a range of ±2000 (V, mV etc). Why 2000 and not ±10 000 which

would be a more convenient range? Simply because a cheap 12 bit converter is used,

which has a range of ±2048 counts.

We usually have more than one channel to digitize. For three component stations there

are 3, while for telemetric networks or small arrays, there might be up to 100 channels.

The simplest approach is to have one ADC for each channel. However, this might be

overkill depending on the application and in addition quite expensive. There are several

ADC cards for PC’s (and other computers) on the market that have up to 64 channels

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