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Chapter 5. Trio Class of Service

Chapter 5. Trio Class of Service

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Intelligent Class Aware Hierarchical Rate Limiters

This feature lets Trio PFEs honor user configured rate limit (shaping) policies for

multiple classes of traffic, while at the same time protecting conforming highpriority traffic from low-priority traffic bursts. This is accomplished though support of up to four levels of scheduling and queuing (Ports/IFL sets/IFLs/Queues),

with support for a shaping rate (PIR), a guaranteed rate (CIR), and excess rate

control at all levels.

Additionally, you have great flexibility as to the attachment points for hierarchical

scheduling and shaping, to include IFDs (ports), IFLs (logical interfaces), and interface sets (which are collections of IFLs or VLANs, and the key enabler of H-CoS).

Priority-Based Shaping

This feature allows you to shape traffic at an aggregate level based on its priority

level, either at the port or IFL-set levels. Priority-based shaping is well suited to

broadband aggregation where large numbers of individual flows are combined into

larger class-based aggregates, which can now be shaped at a macro level.

Dynamic Priority Protection

Priority inheritance combined with the ability to demote or promote the priority

of a traffic class protects bandwidth of high-priority traffic even in the presence of

bursty low-priority traffic.

Highly Scalable CoS

Trio PFEs offer scalable CoS that ensures your hardware investment can grow to

meet current and future CoS need. Key statistics include up to 512k queues per

MPC slot, up to 64k VLANs with eight queues attached per MPC slot, and up to

16k VLAN groups per MPC slot.

Dynamic CoS Profiles

Dynamic CoS allows MX platforms to provide a customized CoS profile for

PPPOE/DHCP/L2TP, etc. Subscriber access where RADIUS authentication extension can include CoS parameters that, for example, might add an EF queue to a

triple play subscriber for the duration of some special event.



Port versus Hierarchical Queuing MPCs

In general, MX routers carry forward preexisting Junos CoS capabilities while adding

numerous unique capabilities. Readers looking for a basic background in Junos CoS

capability and configuration are encouraged to consult the Juniper Enterprise Routing

book. From a CoS perspective, Trio-based MX platforms support two categories of line

cards, namely, those that do only port-level CoS and those that can provide hierarchical

CoS (H-CoS). The latter types provide fine-grained queuing and additional levels of

scheduling hierarchy, as detailed later, and are intended to meet the needs of broadband

subscriber access where CoS handling is needed for literally thousands of users.

Port-based queuing MPCs support eight queues (per port) and also provide port-level

shaping, per-VLAN (IFL) classification, rewrites, and policing.

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Port-based MPC types include:

MX-MPC3E-3D

MPC-3D-16XGE-SFPP

MPC-3D-16XGE-SFPP-R-B

MX-MPC1-3D

MX-MPC1-3D-R-B

MX-MPC2-3D

MX-MPC2-3D-R-B

Hierarchical queuing MPCs support all port-level CoS functionality in addition to

H-CoS, which adds a fourth level of hierarchy via the addition of an IFL set construct.

Only H-CoS capable MPCs have the dense queuing block, which is currently facilitated

by the QXASIC. H-CoS-capable MPCs include:

MX-MPC1-Q-3D

MX-MPC1-3D-Q-R-B

MX-MPC2-Q-3D

MX-MPC2-3D-Q-R-B

MX-MPC2-EQ-3D

MX-MPC2-3D-EQ-R-B

This chapter demonstrates use of shell commands to illustrate operation

and debugging steps. These commands are not officially supported and

should only be used under guidance of JTAC. Incorrect usage of these

commands can be service impacting.



A show chassis hardware command can be used to confirm of a MPC supports H-CoS;

such MPCs are designated with a “Q”:

{master}[edit]

jnpr@R1-RE0# run show chassis hardware

Hardware inventory:

Item

Version Part number

Chassis

Midplane

REV 07

760-021404

FPM Board

REV 03

760-021392

PEM 0

Rev 02

740-017343

Routing Engine 0 REV 07

740-013063

Routing Engine 1 REV 07

740-013063

CB 0

REV 03

710-021523

CB 1

REV 10

710-021523

FPC 2

REV 15

750-031088

. . .



Serial number

JN111992BAFC

TR5026

KE2411

QCS0748A002

1000745244

9009005669

KH6172

ABBM2781

YR7184



Description

MX240

MX240 Backplane

Front Panel Display

DC Power Entry Module

RE-S-2000

RE-S-2000

MX SCB

MX SCB

MPC Type 2 3D Q



If there is ever any doubt, or if you are not sure how many QX chips your Trio MPC

supports, you can access the MPC via VTY and display the dense queuing block’s driver.

If driver details are returned, the card should be H-CoS capable. In the v11.4R1 release,

the show qxchip driver command is used, where n refers to the buffer manager



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number, which currently is either 0 or 1 as some MPC types support two buffer management blocks:

{master}[edit]

jnpr@R1-RE0# run start shell pfe network fpc2

NPC platform (1067Mhz MPC 8548 processor, 2048MB memory, 512KB flash)

NPC2(R1-RE0 vty)# NPC2(R1-RE0 vty)# show qxchip 0 driver

QX-chip : 0

Debug flags

: 0x0

hw initialized

: TRUE

hw present

: TRUE

q-drain-workaround

: Disabled

periodics enabled

: TRUE

rldram_size

qdr_size



L1

L2

L3

Q



: 603979776

: 37748736

Scheduler 0

Allocated

Maximum

------------------3

63

5

4095

8

8191

64

65532



Q Forced drain workaround Counter :

Q Forced drain workaround time:

0

Q BP drain workaround Counter :

4

Q stats msb notification count:

0

ISSU HW sync times:

0 ms

sched block:

0 ms

drop block:

0 ms

Drain-L1 node:

0 (sched0)

64

Drain-L2 node:

0 (sched0)

4096

Drain-L3 node:

0 (sched0)

16384

Drain-base-Q :

0 (sched0) 131072



Scheduler 1

Allocated

Maximum

------------------3

63

3

4095

3

8191

24

65532

0

us



(sched1)

(sched1)

(sched1)

(sched1)



To provide contrast, this output is from a nonqueuing MPC:

--- JUNOS 12.1R1.9 built 2012-03-24 12:52:33 UTC

jnpr@R3>show chassis hardware

Hardware inventory:

. . .

FPC 2

REV 14

750-031089

YF1316

. . .

NPC2(R3 vty)# show qxchip 0 driver

QXCHIP 0 does not exist



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MPC Type 2 3D



H-CoS and the MX80

The MX5, 10, 40, and 80 platforms each contain a built-in routing engine and one

Packet Forwarding Engine (PFE). The PFE has two “pseudo” Flexible PIC Concentrators (FPC 0 and FPC1). H-CoS is supported on these platforms, but currently only for

the modular MIC slots labeled MIC0 and MIC1, which are both housed in FPC1. HCoS is not supported on the four fixed 10xGE ports (which are usable on the MX40

and MX80 platforms), which are housed in FPC0.

H-CoS is not supported on the MX80-48T fixed chassis.



CoS versus QoS?

Many sources use the terms CoS and QoS interchangeably. To try and bring order to

the cosmos, here CoS is used for the net effect, whereas QoS is reserved for describing

individual parameters, such as end-to-end delay variation (jitter). The cumulative effects of the QoS parameters assigned to a user combine to form the class of service

definition. Taking air travel as an example, first class is a class of service and can be

characterized by a set of QoS parameters that include a big comfy seat, metal tableware,

real food, etc. Different air carriers can assign different values to these parameters (e.g.,

better wines, more seat incline, etc.) to help differentiate their service levels from other

airlines that also offer a first class service to try and gain a competitive advantage.



CoS Capabilities and Scale

Table 5-1 highlights key CoS capabilities for various MPC types.

Table 5-1. MPC CoS Feature Comparison.

Feature



MPC1, MPC2,

16x10G MPC



Queuing



MPC1-Q



MPC2-Q



MPC2-EQ



Eight queues per port



Eight queues per port

and eight queues per

VLAN



Eight queues per port

and eight queues per

VLAN



Eight queues per port

and eight queues per

VLAN



Port Shaping



Yes



Yes



Yes



Yes



Egress Queues



8 queues per port



128 k (64 k Ingress/64 k

Egress)



256 k (128 k Ingress/

128 k Egress)



512 K



Interface-sets (L2

scheduling nodes)



NA



8K



8K



16 K



Queue Shaping,

Guaranteed Rate,

and LLQ



CIR/PIR/LLQ



CIR/PIR/LLQ



CIR/PIR/LLQ



CIR/PIR/LLQ



VLAN shaping (perunit scheduler)



NA



CIR/PIR



CIR/PIR



CIR/PIR



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MPC1, MPC2,

16x10G MPC



MPC1-Q



MPC2-Q



MPC2-EQ



Interface Set Level

Shaping



NA



CIR/PIR



CIR/PIR



CIR/PIR



WRED



Four profiles, uses Tail

RED



Four profiles, uses Tail

RED



Four profiles, uses Tail

RED



Four profiles, uses Tail

RED



Rewrite



MPLS EXP, IP Prec/

DSCP (egress or ingress), 802.1p inner/

outer



MPLS EXP, IP Prec/DSCP

(egress or ingress),

802.1p inner/outer



MPLS EXP, IP Prec/DSCP

(egress or ingress),

802.1p inner/outer



MPLS EXP, IP Prec/

DSCP (egress or ingress), 802.1p inner/

outer



Classifier (per

VLAN/IFL)



MPLS EXP, IP Prec/

DSCP, 802.1p (inner

and outer tag), MultiField



MPLS EXP, IP Prec/

DSCP, 802.1p (inner

and outer tag), MultiField



MPLS EXP, IP Prec/

DSCP, 802.1p (inner

and outer tag), MultiField



MPLS EXP, IP Prec/

DSCP, 802.1p (inner

and outer tag), MultiField



Policer per VLAN/

IFL



Single rate two-color,

srTCM, trTCM, hierarchical



Single rate two-color,

srTCM, trTCM, hierarchical



Single rate two-color,

srTCM, trTCM, hierarchical



Single rate two-color,

srTCM, trTCM, hierarchical



Feature



Queue and Scheduler Scaling

Table 5-2 lists supported queue and subscriber limits for Trio MPCs. Note that the

supported IFL numbers are per PIC. On PICs with multiple ports, the IFL counts should

be dived among all ports for optimal scaling.

Table 5-2. MPC Queue and Subscriber Scaling.

MPC Type



Dedicated

Queues



Subscribers/

IFLs



IFLs: Four Queues



IFLs: Eight Queues



30-Gigabit Ethernet Queuing



64 k



16 Kk



16 k (8 k per PIC)



8 k (4 k per PIC)



128 k



32 k



32 k (8 k per PIC)



16 k (4 k per PIC)



512 k



64 k



64 k (16 k per PIC)



64 k (16 k per PIC)



MPC (MPC1-3D-Q)

60-Gigabit Ethernet Queuing

MPC (MPC2-3D-Q)

60-Gigabit Ethernet Enhanced Queuing

MPC (MPC2-3D-EQ)



Table 5-3 summarizes the currently supported scale for H-CoS on fine-grained queuing

MPCs as of the v11.4R1 Junos release.

Capabilities constantly evolve, so always check the release notes and

documentation for your hardware and Junos release to ensure you have

the latest performance capabilities.



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Table 5-3. Queue and Scheduler Node Scaling.

Feature



MPC1-Q



MPC2-Q



MPC2-EQ



Queues (Level 4)



128 k (split between ingress/

egress



256 k (split between ingress/

egress)



512 k



IFLs (Level 3)



Four queues: 16 k/8 k per PIC



Four queues: 32 k/8 k per PIC



Eight queues: 8 K/4 k per PIC



Eight queues: 16 K/4 k per PIC



Four or eight queues:

64 k/16 k per PIC



IFL-Set nodes (Level 2)



8k



16 k



16 k



Port nodes (Level 1)



128



256



256



Though currently only egress queuing is supported, future Junos releases may support

ingress queuing in an evolution path similar to the previous IQ2E cards, which also

provided H-CoS. Note how the Q-type MPCs divide the pool of queues with half dedicated to ingress and egress pools, respectively. In contrast, the EQ MPC can use all 512

k queues for egress, or it can split the pool for ingress and egress use. Note again that

in the v11.4R1 release, ingress queuing is not supported for Trio MPCs.

How Many Queues per Port? Knowing how many queues are supported per MPC and MIC

is one thing. But, given that many MICs support more than one port, the next question

becomes, “How many queues do I get per port?” The answer is a function of the number

of Trio PFEs that are present on a given MPC.

For example, 30-gigabit Ethernet MPC modules have one PFE, whereas the 60-gigabit

Ethernet MPC modules have two. Each PFE in turn has two scheduler blocks that share

the management of the queues. On the MPC1-3D-Q line cards, each scheduler block

maps to one-half of a MIC; in CLI configuration statements, that one-half of a MIC

corresponds to one of the four possible PICs, numbered 0 to 3. MIC ports are partitioned equally across the PICs. A two-port MIC has one port per PIC. A four-port MIC

has two ports per PIC.

Figure 5-1 shows the queue distribution on a 30-gigabit Ethernet queuing MPC module

when both MPCs are populated to support all four PICs.



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Figure 5-1. Queue Distribution on MPC1-3D-Q: Four PICs.



Figure 5-2. Queue Distribution on MPC1-3D-Q: Two PICs.



When all four PICs are installed, each scheduler maps to two PICs, each of which is

housed on a different MIC. For example, scheduler 0 maps to PIC 0 on MIC 0 and to

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PIC 2 on MIC 1, while scheduler 1 maps to PIC 1 on MIC 0 and to PIC 3 on MPC 1.

One-half of the 64,000 egress queues are managed by each scheduler.

In this arrangement, one-half of the scheduler’s total queue complement (16 k) is available to a given PIC. If you allocate four queues per IFL (subscriber), this arrangement

yields 4 k IFLs per PIC; if desired, all PIC queues can be allocated to a single PIC port

or spread over IFLs assigned to multiple PIC ports, but you cannot exceed 16 k queues

per PIC. A maximum of 2 k IFLs can be supported per PIC when using eight queues

per IFL.

Figure 5-2 shows another possible PIC arrangement for this MPC; in this case, one MIC

is left empty to double the number of queues available on the remaining MIC.



Figure 5-3. Queue Distribution on the 60-Gigabit Ethernet Queuing MPC Module.



By leaving one MIC slot empty, all 32 k queues are made available to the single PIC

that is attached to each scheduler block. This arrangement does not alter the total MPC

scale, which is still 16 k IFLs using four queues per subscriber; however, now you divide

the pool of queues among half as many PICs/ports, which yields twice the number of

subscribers per port, bringing the total to 8 k IFLs per PIC when in four-queue mode

and 4 k in eight-queue mode.

On 60-gigabit Ethernet queuing and enhanced queuing Ethernet MPC modules, each

scheduler maps to only one-half of a single MIC: PIC 0 or PIC 1 for the MIC in slot 0

and PIC 2 or PIC 3 for the MIC in slot 1. Figure 5-3 shows how queues are distributed

on a 60-gigabit ethernet enhanced queuing MPC module.

Of the 512,000 egress queues possible on the module, one-half (256,000) are available

for each of the two Packet Forwarding Engines. On each PFE, half of these queues

(128,000) are managed by each scheduler. The complete scheduler complement

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(128,000) is available to each PIC in the MIC. If you allocate all the queues from a

scheduler to a single port, then the maximum number of queues per port is 128,000.

If you dedicate four queues per subscriber, you can accommodate a maximum of 32,000

subscribers on a single MPC port. As before, half that if you provision eight queues per

subscribers, bringing the maximum to 16,000 subscribers per MPC port.

The number of MICs installed and the number of ports per MIC does not affect the

maximum number of queues available on a given port for this MPC type. This module

supports a maximum of 64,000 subscribers regardless of whether you allocate four or

eight queues per PIC. The MPC supports a maximum of 128,000 queues per port. If

you have two two-port MICs installed, each PIC has one port and you can have 128,000

queues on each port. You can have fewer, of course, but you cannot allocate more to

any port. If you have two four-port MICs installed, you can have 128,000 queues in

each PIC, but only on one port in each PIC. Or you can split the queues available for

the PIC across the two ports in each PIC.

Configure Four- or Eight-Queue Mode. Given that all Trio MPCs support eight queues, you

may ask yourself, “how do I control how many queues are allocated to a given IFL?”

Simply defining four or fewer forwarding classes (FCs) is not enough to avoid allocating

eight queues, albeit with only four in use. When a four FC configuration is in effect,

the output of a show interfaces queue command displays Queues supported: 8, Queues

in use: 4, but it’s important to note that the scheduler node still allocates eight queues

from the available pool. To force allocation of only four queues per IFL, you must

configure the maximum queues for that PIC as four at the [edit chassis] hierarchy:

jnpr@R1-RE0# show chassis

redundancy {

graceful-switchover;

}

. . .

fpc 2 {

pic 0 {

max-queues-per-interface 4;



Changing the number of queues results in an MPC reset.



Low Queue Warnings. An SNMP trap is generated to notify you when the number of available dedicated queues on a MPC drops below 10%. When the maximum number of

dedicated queues is reached, a system log message, COSD_OUT_OF_DEDICATED_QUEUES, is

generated. When the queue limit is reached, the system does not provide subsequent

subscriber interfaces with a dedicated set of queues.

If the queue maximum is reached in a per unit scheduling configuration, new users get

no queues as there are simply none left to assign. In contrast, with a hierarchical scheduling configuration, you can define remaining traffic profiles that can be used when the

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maximum number of dedicated queues is reached on the module. Traffic from all affected IFLs is then sent over a shared set of queues according to the traffic parameters

that define the remaining profile.



Why Restricted Queues Aren’t Needed on Trio

Defining restricted queues at the [edit class-of-service restricted-queues] hierarchy is never necessary on Trio MPCs. The restricted queue feature is intended to support a CoS configuration that references more than four FCs/queues on hardware that

supports only four queues. The feature is not needed on Trio as all interfaces support

eight queues.



Trio versus I-Chip/ADPC CoS Differences

Table 5-4 highlights key CoS processing differences between the older IQ2-based

ADPC-based line cards and the newer Trio-based MPCs.

Table 5-4. ADPC (IQ2) and MPC CoS Compare and Contrast.

Feature



DPC-non-Q



DPCE-Q



MPC



Packet Granularity



64 B



512 B



128 B



Default Buffer



100 ms



500 ms



100 ms port based

500 ms for Q/EQ



Buffer Configured



Minimum



Maximum



Maximum



WRED



Head, with Tail assist



Tail Drop



Tail Drop



Port Level Shaping



NA



Supported



Supported



Queue Level Shaping



Single Rate



NA



Dual Rate per Queue



Egress mcast filtering



NA



NA



Supported



Egress Filter



Match on ingress protocol



Match on ingress protocol



Match on egress protocol



Overhead Accounting



Layer 2



Layer 2



Layer 1



Some key CoS differences between Trio-based Ethernet MPC and the I-chip-based

DPCs include the following:

A buffer configured on a 3D MPC queue is treated as the maximum. However, it

is treated as the minimum on an I-chip DPC. On port-queuing I-chip DPCs, 64

byte-per-unit dynamic buffers are available per queue. If a queue is using more than

its allocated bandwidth share due to excess bandwidth left over from other queues,

its buffers are dynamically increased. This is feasible because the I-chip DPCs primarily perform WRED drops at the head of the queue, as opposed to “tail-assisted”

drops, which are performed only when a temporal buffer is configured or when

the queue becomes full. When a temporal buffer is not configured, the allocated

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buffer is treated as the minimum for that queue and can expand if other queues

are not using their share.

The Junos Trio chipset (3D MPC) maintains packets in 128-byte chunks for processing operations such as queuing, dequeuing, and other memory operations. JCell size over the fabric remains at 64 B.

Port shaping is supported on all MPCs.

Queues can have unique shaping and guaranteed rate configuration.

On MPCs with the Junos Trio chipset, WRED drops are performed at the tail of

the queue. The packet buffer is organized into 128-byte units. Before a packet is

queued, buffer and WRED checks are performed, and the decision to drop is made

at this time. Once a packet is queued, it is not dropped. As a result, dynamic buffer

allocation is not supported. Once the allocated buffer becomes full, subsequent

packets are dropped until space is available, even if other queues are idle.

To provide larger buffers on Junos Trio chipset Packet Forwarding Engines, the

delay buffer can be increased from the default 100 ms to 200 ms of the port speed

and can also be oversubscribed using the delay-buffer-rate configuration on a per

port. ADPC line cards base their shaping and queue statistics on Layer 2, which

for untagged Ethernet equates to an additional 18 bytes of overhead per packet

(MAC addresses, Type code, and FCS). In contrast, Trio chip sets compute queue

statistics on Layer 1, which for Ethernet equates to an additional 20 bytes in the

form of the 8 byte preamble and the 12 byte inter-packet gap. Note that Trio RED

drop statistics are based on Layer 2 as the Layer 1 overhead is not part of the frame

and is therefore not stored in any buffer.



Trio CoS Flow

Note that general packet processing was detailed in Chapter 1. In this section, the focus

is on the specific CoS processing steps as transit traffic makes its way through a MX

router’s PFE complex. Figure 5-4 shows the major CoS processing blocks that might

be present in a Trio PFE.



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