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7 Single/Dual Rail Conversion Circuits

# 7 Single/Dual Rail Conversion Circuits

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Single/Dual Rail Conversion Circuits

469

ure 9.49. A straightforward approach to solving this problem is to use a differential amplifier circuit.

Differential Amplifier

The differential amplifier accepts two input voltages

depends upon the difference

and

and produces an output voltage that

This type of circuit can be used to convert a dual-rail logic signal back into a single-rail value that

can be interfaced with standard logic circuits.

A basic differential amplifier is shown in Figure 9.50. This uses a source-coupled pair of nFETs

Mn1 and Mn2 as the input devices. The pFETs Mp1 and Mp2 are used as active-load devices to

provide a pull-up path to the power supply voltage

A single output voltage is shown; it is a

single-rail variable corresponding to the value associated with the input voltage

The output

voltage is determined by the current

as it produces a voltage drop across Mp2. To analyze the

circuit, assume that the nFETs are both in saturation. The currents

and

are given by

where we will assume that Mn1 and Mn2 have the same aspect ratio so that

the source, the currents must sum to

applies to both. At

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due to the current source there. The behavior of the circuit revolves around finding

and

as

functions of the difference voltage

Let us calculate the currents by first noting that both nFETs have the same source voltage, so that

provides the important relationship between the input voltages

Next, we may rearrange the expression for

and

to give

and

and the current equations.

so that

This may be used to find the desired relations. For example,

Squaring both sides gives

may be eliminated by writing

Single/Dual Rail Conversion Circuits

471

Expanding and simplifying,

which, upon squaring and rearrangement, gives

This is a quadratic equation for

with a solution of

where we have chosen the positive root to insure that

is found to be

It is seen by inspection that

increases as

Also note that when

increases. Similarly, the

corresponding to

This corresponds to equal inputs giving balanced current flow.

The general behavior of both currents

and

are shown in Figure 9.51. As

increases

from a negative number

to a positive value

increases from 0 to the maximum value of

while

has the opposite behavior. The value of the difference voltage

needed to obtain

can be calculated by setting

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which is a quartic for

Solving for

and then taking the square root gives the value as

The same approach can be used to show that

gives

is

so that the total voltage change needed to divert the current from one FET to the other

This shows that the width of the input transition is set by the ratio of

for the circuit design since

This provides a basis

can be chosen according to the value of

9.7.3 A Basic Current Source

The above analysis shows that the sensitivity of the differential amplifier depends upon the value of

the current source

Although several types of current source circuits have been published in the

literature, the simple one illustrated in Figure 9.52 illustrates the important points. This circuit uses

a FET MnC to provide the current. It is biased with a gate-source voltage of

where

is a reference voltage supplied by the voltage divider circuit made up of MpR and MnR. Assuming that

MnC is biased into saturation, we can estimate

Problems

473

Channel length modulation effects may be included by multiplying this expression by the factor

To determine the value of

first note that MpR is defined by the terminal voltages

while the nFET MnR has

This shows that both transistors are saturated, so equating drain currents gives

Rearranging gives

This shows that the ratio

can be used to set

which in turn biases MnC to provide

The alert reader will have noticed that this identical to the formula for the inverter threshold voltage

this is due to the fact that the voltage divider circuit made up of MnR and MpR is simply an

inverter with the input shorted to the output!

9.8 Problems

[9-1] Design the CVSL logic gate for the function

and its complement using the AOI/OAI logic network design approach.

[9-2] Design the CVSL logic gate for the function

and its complement using the AOI/OAI logic network design approach.

[9-3] Design the CVSL logic gate for the function

using AOI/OAI design approach.

[9-4] Create the CVSL logic tree network for the 2-input function described by the table shown in

Figure P9.1.

[9-5] Design the CVSL gate by using the function in Figure P9.2 to construct the logic tree.

[9-6] Design the CVSL gate by using the information provided in the truth table of Figure P9.3 to

construct the logic tree for the function G and

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[9-7] Consider the logic function

(a) Construct the function table for this function using a horizontal format where the output F

and the input variables are in one column with the top-to-bottom order of F, A, B, C.

(b) Construct the CVSL logic tree as discussed in the text.

[9-8] Use 2-input CPL arrays to implement the NAND4

[9-9] Use CPL gates to construct the circuit for the logic function

and its complement.

[9-10] Create the DPL circuit for the odd function

and its complement using basic DPL cascades. Then compare your circuit with the CPL equivalent

by looking at device count and electrical operation.

References

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9.9 References

[1] K.M. Chu and D.L. Pulfrey, “A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic,” IEEE J. Solid-State Circuits, vol. SC-22,

no. 4, pp. 528-532, August, 1987.

[2] K.M. Chu and D.L, Pulfrey, “Design Procedures for Differential Cascode Voltage Switch Logic

Circuits,” IEEE J. Solid-State Circuits, vol. SC-21, no. 4, pp. 1082-1087, December, 1986.

[3] T. A. Grotjohn and B. Hoefflinger, “Sample-Set Differential Logic (SSDL) for Complex HighSpeed VLSI,” IEEE J. Solid-State Circuits, vol. SC-21, no. 2, pp. 367-369, April, 1986.

[4] L.G. Heller, et al., “Cascode voltage switch logic: a differential CMOS logic family, ISSCC84

Digest, pp. 16-17, February, 1984.

[5] N. Kanopoulos and N. Vasanthavada, “Testing of Differential Cascode Voltage Switch (DCVS)

Circuits,” IEEE J. Solid-State Circuits, vol. SC-25, no. 3, pp. 806-812, June, 1990.

[6] F-S. Lai and W. Hwang, “Design and Implementation of Differential Cascode Voltage Switch

with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems,” IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 563-573, April, 1997.

[7] S-H. Lu, “Implementation of Iterative Networks with CMOS Differential Logic,” IEEE J.

Solid-State Circuits, vol. 23, no. 4, pp. 1013-1017, August, 1988.

[8] D. Somasekhar and K. Roy, “Differential Current Switch Logic: A Low Power DCVS Logic

Family,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 981-991, July, 1996.

[9] M. Suzuki, et al., “A 1.5ns 32-b CMOS ALU in Double Pass-Transistor Logic,” IEEE J. SolidState Circuits, vol. 28, no. 11, pp. 1145-1151,November, 1993.

[10] K. Yano, et al., “A 2.8-ns CMOS 16xl6-b Multiplier Using Complementary Pass-Transistor

Logic,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp.388-395, April, 1990.

Chapter 10

Issues in Chip Design

Designing a CMOS integrated circuit requires more than just understanding the

logic circuits. Items such as interconnect delay on the chip, and interfacing the circuit to the outside world require special considerations. In this chapter we will

study some important circuit problems that occur at the chip level and affect the

internal operations. The introduction here is designed to provide a solid background for more specialized studies.

10.1 On-Chip Interconnects

It is interesting to examine the evolution of MOS technology in recent years. The typical channel

length in a transistor has shrunk to a nominal value of less than 0.2 microns using the best manufacturing technology. With this type of resolution, the footprint area required for an FET has shrunk to

the point where it is almost insignificant when compared with the surface area needed for contacts,

vias, and interconnect routing. This leads to the conclusion that modern CMOS chip design is

interconnect-limited. In other words, we usually don’t worry about the number of FETs on a chip;

in most cases, the wiring complexity is much more important to the real estate consumption.

Modern CMOS process flows provide several metal layers for use as interconnect wiring.

Although 3 or 4 interconnect layers were sufficient for networks with a million or so FETs, the

high-density compact systems being designed at the start of the 21st century require the use of 7-to10 or more interconnect layers. Obviously, accurate modelling of on-chip wiring is important to the

circuit designer. Parasitic-induced delays and stray coupling may require “tweaking” or re-design at

the circuit level to make a chip operational. We will therefore direct our attention to this important

topic from the viewpoint of electrical modelling of the interconnect structures.

10.1.1 Line Parasitics

Let us examine the basic geometry shown in Figure. 10.1. This is representative of an interconnect

line that is described by a width w, and has a distance of d. The material layer itself has a height (or

thickness) h. Parasitic electrical elements include resistance and capacitance; although the wire also

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has inductance associated with it, we usually do not encounter magnetic effects at local circuit

level.1 Our program at this point is two-fold. First, we want to determine the values of the parasitic

elements that are introduced by the interconnect. Once these have been calculated, we can then proceed to evaluate their effects on the performance.

Line Resistance

The resistance of the line from one end to the other is computed by using the standard equation

where is the resistivity in units of

and A =hw is the cross-sectional area of the line. Every

material is characterized by a value of When choosing interconnect lines, metals dominate due to

their small values of resistivity. Although this expression can be used directly, a more useful formulation for use in chip design is based on the use of the sheet resistance which has units of ohms

for the layer. This is defined by

and is the end-to-end resistance of a square section of material wit d = w as seen from the top. The

sheet resistance is useful as it can be directly measured on a test structure in the laboratory. Once

is known, then the total resistance of a line that has a width w and spans a distance d is given by

where

1

This is due to the small current flow levels. One exception (among several) to this statement are the power

supply and ground lines, which can exhibit inductive effects. For example, if the current changes very quickly

in a power supply line then there is a temporary voltage drop of v=L(di/dt) on the line, which reduces the voltage reaching the circuit.

On-Chip Interconnects

479

is the number of squares of dimensions (w × w ) encountered by the current. This can be seen by

the top view of the interconnect shown in Figure 10.2. Owing to this observation,

is sometimes

labeled as having units of “ohms per square” in processing jargon.It is worthwhile to note that the

sheet resistance is quite sensitive to the height h of the interconnect. As the minimum linewidth has

decreased, the thickness of the material layer has remained fairly large. In fact, most of the interconnects in a state-of-the art process are thicker than they are wide.

Example 10-1

Doped polysilicon has a best-case sheet resistance of about 20-to-25 per square. Consider a poly

line that has a width of 0.4

and a length of 20

. The number of squares of size (0.4

x 0.4

is

so with

we have a line resistance of

To show the relative significance of this results, consider an nFET with

an aspect

ratio of 10, and a threshold voltage of 0.7 volts. With a 3.3v power supply, the linearized resistance

is

so that the line resistance is about five times larger than the FET drain-source resistance. If we used

this type of interconnect at the output of a logic gate, the parasitic resistance would dominate the

delay times.

Line Capacitance

The capacitance of an interconnect line can be the limiting factor in high-speed signal transmission.

Consider the cross-sectional geometry shown in Figure 10.3(a). Most formulations are based on the

capacitance per unit length c’ with units of farads per centimeter such that the total capacitance of

the line in farads is given by

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