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Figure 28. FDA2100LV communication bus interaction scheme

Figure 28. FDA2100LV communication bus interaction scheme

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Integrated step-up



FDA2100LV



7



Integrated step-up



7.1



Functional description

The FDA2100LV a integrates a step-up with following purposes:

1. To increase the 14.4 V typical car-radio battery voltage up to 25 V to get higher audio

power on the standard 4 ohm load

2. With a proper application circuit, to maintain a voltage higher than the battery in case of

car-radio battery voltage drop (i.e. start-stop event) across the PWM audio amplifier.

The step-up driver output (gate-drive) is connected to an external PowerMOS M which, with

the coil L2 and the diode D, it realizes the standard step-up circuitry.

The pin Comp is connected to the capacitor C7, responsible of the system gain/stability.

The output voltage feedback of the Step-Up is internally connected to the pin A-vdd.

The step-up clock frequency is the same as of the PWM amplifier output clock.

Through the pins I1, I2, the voltage across the current sensor R7 is monitored.

If VR7 >V(Ilim), a current limiting is activated.

Thanks to the low-pass filter R5 and C5, the current limiting works on the average value.

A current limiting activation flag is available on the I2C bus DB1 - D7.



7.2



Step-up settings

Through I2C bus, it is possible to select the following different step-up settings:



Step-up enable/disable



Output voltage selection (18 V, 20 V, 22.5 V, 25 V)



Step-up always on or turned off @ Tchip > 150 °C and on again @ Tchip < 135 °C



Step-up soft start selection time (2 ms, 5 ms, 10 ms).



Higher time is recommended because reduces the turn-on peak current



Step-up clock dithering (on/off).

Dithering spreads the harmonics produced by the step-up square wave, reducing the

peak amplitude (5 -10 dB).



Maximum ton of the external PowerMOS selection.

This function is needed to avoid a too large current flowing in the PowerMOS in case of

low battery voltage.

In case of low battery voltage the step-up output voltage is no more regulated by the

feedback but depends only by the input voltage and the duty cycle D = ton/(ton + toff) of

the external PowerMOS.

In the following table ton versus the I2C selection at different I2S sync clock is shown.

Table 12. Step up settings



7.3



IB4 – D0, D1



Fclock 35 kHz - 50 kHz



Fclock = 96 kHz and 192 kHz



00 – Min



0.0586 / fclock



1.22 µs



01 – Med



0.0664 / fclock



1.38 µs



10-11 - Max



0.0742 / fclock



1.55 µs



Turn-on procedure

The step-up must be enabled through I2C bus together with or after the PWM power

amplifiers. It is not allowed to enable the step-up before the PWM power amplifiers.



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8



Application schematics



Application schematics

Figure 17. Application schematic with step-up























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Low voltage (“start stop”) operation



9



FDA2100LV



Low voltage (“start stop”) operation

The most recent OEM specification are require automatic stop of a car engine at traffic light,

in order to reduce emissions of polluting substances. Thanks to its innovating design, the

FDA2100LV allows a continuous operation when battery falls down to 6/7V during such

conditions, without producing pop noise. The maximum system power will be reduced

accordingly.

Worst case battery cranking curves are shown below, indicating the shape and duration of

allowed battery transitions

Figure 19. Worst case battery cranking curve sample 1

6BATT6

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V1 = 12 V; V2 = 6 V; V3 = 7 V; V4 = 8 V

t1 = 2 ms; t2 = 50 ms; t3 = 5 ms; t4 = 300 ms; t5 =10 ms; t6 = 1 s; t7 = 2 ms

Figure 20. Worst case battery cranking curve sample 2

6BATT6

6



6

6



T



T T



T



V1 = 12 V; V2 = 6 V; V3 = 7 V

t1 = 2 ms; t2 = 5 ms; t3 = 15 ms; t5 = 1 s; t6 = 50 ms



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I2S bus interface



FDA2100LV



10



I2S bus interface

The FDA2100 accepts the I2S standard format that could be Time Division Multiplexed

(TDM).

I2S bus is made up of three lines: the clock lines (SCK), the sync line (WS) and serial data

line (SD) where 32 bits words are sent.

Note that only the first 20 bits received per word are processed and that WS frequency has

to be always the same as audio sampling frequency ƒs.

According to I2C settings, audio signals can be sent with the following data format:





I2S standard







TDM 4 channels mode 1







TDM 4 channels mode 2







TDM 8 channels mode 1







TDM 8 channels mode 2







TDM 8 channels mode 3







TDM 8 channels mode 4

Figure 21. I2S standard data format

FS

XFS

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I2S bus interface



FDA2100LV



TDM 4 channels





2 devices, 4 channels driven with 1 data lines







2 bits to properly receive data:









IB1[5-4] bits to recognize TDM4 channels and TDM4 modes 1 or 2



For each channel, the serial data is transmitted with the MSB first

Figure 22. TDM4 data format

TH MAX

TH MIN

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TDM 8 channels





4 devices, 8 channels driven with 1 data lines







4 bits to properly receive data:











IB1[5-4] bits to recognize TDM8 channels







IB4[7-6] bits to select TDM8 mode for channel selection



For each channel, the serial data is transmitted with the MSB first.

Figure 23. TDM8 data format

TH MAX

H

TH MIN

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Rev 1



I2S bus interface



FDA2100LV



I2S Standard format

Refer to I2S bus specification for details and timing



TDM format





WS changes on falling edge of SCK, one clock period before the MSB is transmitted.







WS does not need to be symmetrical, min duration is two period of SCK, max duration

is as here specified:











th,max = 127 TSCK in TDM 4 channels







th,max = 255 TSCK in TDM 8 channels



For other timing, refer to I2S bus specification



I2S Interface configuration: IB1[5-4], IB4[7-6]

IB1[5-4] IB4[7-6]

00

xx



I2S standard



01



xx



TDM 4ch mode 1



10



xx



TDM 4ch mode 2



11



00



TDM 8ch mode 1



11



01



TDM 8ch mode 2



11



10



TDM 8ch mode 3



11



11



TDM 8ch mode 4

Figure 24. I2S interface



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Figure 28. FDA2100LV communication bus interaction scheme

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