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Table 5. General and audio characteristics

Table 5. General and audio characteristics

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FDA2100LV



Electrical specifications

Table 5. General and audio characteristics (continued)



Symbol



Parameter

2



2



Test condition



Min.



Typ.



Max.



Unit



I C, I S bus pins

voltage



-



-



-



3.6



V



Venable



Enable pins voltage



-



-



-



5.5



V



CD/Diag



CD/Diag pin voltage



-



-



-



5.5



V



Idvbatt



Total quiescent drain

current pin Vbatt



Device in standby condition



-



-



2



µA



Idvdd



Total quiescent drain

current pins Vdd



Device in standby condition



-



-



5



µA



Idvbatt



Total quiescent drain

current pin Vbatt



Device ON



-



32



40



mA



Idvdd



Total quiescent drain

current pins Vdd



Device ON



-



80



100



mA



RL = 4 Ω; max power Vdd = 15.2 V



42(2)



50(2)



-



W



THD = 10 %



23(2)



29(2)



-



W



RL = 2 Ω; THD 10 %



38(2)



50(2)



-



W



RL = 2 Ω; max power



57(2)



78(2)



-



W



Vdd: 25 V; max power



-



135(2)



-



W



Vdd: 25 V; THD = 10 %



72(2)



80(3)



-



W



Vdd: 30 V; THD = 10 %



100(2)



120(3)



-



W



Vdd: 30 V; max power



-



180(3)



-



W



Total harmonic

distortion



PO = 1 W to 10 W, f = 1 kHz



-



0.03



00.5



%



PO = 1 W to 10 W, f = 10 kHz



-



0.2



0.5



%



CT



Cross talk



f = 1 kHz to 10 kHz



60



80



-



dB



GV1



Voltage gain high



GAIN @ -10 dBFS

44.1-48 and 96 KHz

192 kHz



9.3

11.5



10.3

13



11.3

14.5



Vp



Voltage gain low



GAIN @ -10 dBFS

44.1-48 and 96 KHz

192 kHz



5.5

6.7



6

7.6



6.5

8.5



Vp



Voltage gain match



-



-1



-



1



dB



DR



Dynamic range



-



-



108



-



dB

Awtd(3)



EIN1



Output noise GV = GV1



A-wtd, no output signal



-



75



100



µV



SNR



Signal to noise ratio



A-wtd



-



110



-



dB

A-wtd



SVR



Supply voltage rejection f = 1 kHz; Vr = 1 Vpk;



60



85



-



dB



Mute pin source current -



3



6



9



µA



VI2C, VI2S



PO



THD



GV2

GV1,2



IM



Output power (2)



Rev 1



11/61

60



Electrical specifications



FDA2100LV



Table 5. General and audio characteristics (continued)

Symbol



Parameter



Test condition



Min.



Typ.



Max.



Unit



VMth



Mute pin voltage

threshold



-



1.6



2.2



2.6



V



VMcl



Mute pin internal clamp

voltage



-



4.3



5



5.5



V



AM



Mute attenuation



-



80



100



-



dB



VOS



Offset voltage



Mute and play



-20



-



20



mV



IB5-D4-5 I2C setting = 00

and legacy mode (Min)



5.4



5.7



6.0



V



IB5-D4-5 I2C setting = 01 (Med.)



6.75



7.25



7.75



V



7.8



8.4



9.0



V



IB5-D4-5I2C setting = 00

and legacy mode (Min.)



5.0



5.3



5.7



V



IB5-D4-5 I 2C setting = 01 (Med.)



6.4



6.8



7.2



V



7.5



8.0



8.5



V



-



0.1



0.3



0.5



V



IB5-D6-7 I2C setting = 00

and legacy mode (Min.)



5.4



5.7



6.0



V



-



7.5



-



V



-



8.8



-



V



IB5-D6-7

setting = 00

and legacy mode (Min.)



5.0



5.3



5.7



V



IB5-D6-7 I2C setting = 01 (Med.)



6.4



6.8



7.2



V



7.5



8.0



8.5



V



0.1



0.3



0.5



V



VAMVbatt



Vbatt supply mute

threshold (4)



2C



IB5-D4-5 I



VUVVbatt



Vbatt supply UVLO

threshold (4)



2C



IB5-D4-5 I

VUVhyst



VAMVdd



Vbatt supply UVLO

hysteresis (4)



Vdd supply mute

threshold (4)



setting = 10 - 11 (Max.)



setting = 10 - 11 (Max.)



IB5-D6-7 I2C setting = 01 (Med.)

2C



IB5-D6-7 I



setting = 10 - 11 (Max.)



I2C



VUVVdd



Vdd supply UVLO

threshold (4)



2C



IB5-D6-7 I



setting = 10 - 11 (Max.)



Vbatt supply UVLO

hysteresis (4)



-



CDLK



Clip det high leakage

current



CD off



-



0



15



µA



CDSAT



Clip det sat. voltage



CD on; ICD = 1 mA



-



150



300



mV



Clip det THD



THD@100 Hz with average

Vclipdet = 2 V

(pull-up resistor = 10 k to 3.3 V)



5



10



15



%



TslowM



Slow mute delay



-



85



100



115



ms



TfastM



Fast mute delay



-



1.7



2



2.3



ms



VUVhyst



CD1THD (5)



1. Maximum value at ATE = 25 V with 4 ohm load. 35 V tested w/o load.

2. Test correlated to the RdsON measurement (ATE test).

3. Value measured at bench (not tested at ATE).

4. Tested in 00 configuration only.

5. Not tested at ATE.



12/61



Rev 1



FDA2100LV



Electrical specifications

Table 6. Diagnostics



Symbol



Parameter



Test condition



Min.



Typ.



Max.



Unit



Turn on test (short to GND, short to Vs) current thresholds

Pgnd



No short to GND det. (below this

output current limit, the output is considered in normal conditions)



-



-



3



mA



Pps



No Short to positive Supply det.

(below this output current limit,

the output is considered in

normal conditions)



-



-



-3



mA



Pgnd



Short to GND det. (over this

output current limit, the output is

considered in short circuit to

GND)



30



-



-



mA



Pps



Short to positive Supply det.

(over this output current limit,

the output is considered in short

circuit to VS)



-30



-



-



mA



-



267.5



-



ms



AC-DC load diagnostic test timing

Tlt



Load test time (AC+DC)



Fs = 44.1 kHz



Tac



AC sweep length



-



-



20.5



-



ms



Tdc



DC pulse length



-



-



247



-



ms



Fac



AC test internal signal

generated frequency value



(1)



-



19.3



-



kHz



DC test - Low Gain

Vdc(2)



DC test output amplitude value



Differential signal

Rdc setting = Option 1



0.53



0.58



0.63



V



Vdc(2)



DC test output amplitude value



Differential signal

Rdc setting = Option 2



1.05



1.15



1.25



V



Vdc(2)



DC test output amplitude value



Differential signal

Rdc setting = Option 3



2.11



2.3



2.49



V



Vdc(2)



DC test output amplitude value



Differential signal

Rdc setting = Option 4



0.27



0.29



0.31



V



0.63



-



4.3







DC test - Low Gain - Rsetting = Option 1

Rdcnl



Normal load



DC diagnostic short

threshold selection = 00



Rdcsl



Shorted load



-



-



-



0.4







Open load



DC diagnostic short

threshold selection = 00



17



-



-







1.25



-



8.6







-



-



0.8







34



-



-







Rdcol



DC test - Low Gain - Rsetting = Option 2

Rdcnl



Normal load



DC diagnostic short

threshold selection = 00



Rdcsl



Shorted load



-



Rdcol



Open load



DC diagnostic short

threshold selection = 00



Rev 1



13/61

60



Electrical specifications



FDA2100LV

Table 6. Diagnostics (continued)



Symbol



Parameter



Test condition



Min.



Typ.



Max.



Unit



2.5



-



17







-



-



1.6







68



-



-







0.35



-



2.15







-



-



0.2







DC test - Low Gain - Rsetting = Option 3

Rdcnl



Normal load



DC diagnostic short

threshold selection = 00



Rdcsl



Shorted load



-



Rdcol



Open load



DC diagnostic short

threshold selection = 00



DC test - Low Gain - Rsetting = Option 4 (intended for low ohminc speakers)

Rdcnl



Normal load



DC diagnostic short

threshold selection = 00



Rdcsl



Shorted load



-



Rdcol



Open load



DC diagnostic short

threshold selection = 00



8.5



-



-







AC test - Low Gain

Vac(2)



AC test output amplitude value



Single ended signal

Rac setting = Option 1



0.83



0.9



0.98



Vp



Vac(2)



AC test output amplitude value



Single ended signal

Rac setting = Option 2



1.65



1.8



1.95



Vp



Vac(2)



AC test output amplitude value



Single ended signal

Rac setting = Option 3



3.30



3.6



3.9



Vp



AC test - Low Gain - Rsetting = Option 1

Zmeas(nl)



Normal load



-



-



-



6







Zmeas(ol)



Open load



-



20



-



-







AC test - Low Gain - Rsetting = Option 2

Zmeas(nl)



Normal load



-



-



-



12







Zmeas(ol)



Open load



-



40



-



-







AC test - Low Gain - Rsetting = Option 3

Zmeas(nl)



Normal load



-



-



-



24







Zmeas(ol)



Open load



-



80



-



-







DC test - High Gain

Vdc(2)



DC test output amplitude value



Differential signal

Rdc setting = Option 1



0.9



1



1.1



V



Vdc(2)



DC test output amplitude value



Differential signal

Rdc setting = Option 2



1.81



2



2.19



V



Vdc(2)



DC test output amplitude value



Differential signal

Rdc setting = Option 3



3.61



4



4.39



V



Vdc(2)



DC test output amplitude value



Differential signal

Rdc setting = Option 4



0.45



0.5



0.55



V



14/61



Rev 1



FDA2100LV



Electrical specifications

Table 6. Diagnostics (continued)



Symbol



Parameter



Test condition



Min.



Typ.



Max.



Unit



1.08



-



7.4







-



-



0.68







DC test - High Gain - Rsetting = Option 1

Rdcnl



Normal load



DC diagnostic short

threshold selection = 00



Rdcsl



Shorted load



-



Rdcol



Open load



DC diagnostic short

threshold selection = 00



29



-



-







2.17



-



15







-



-



1.39







DC test - High Gain - Rsetting = Option 2

Rdcnl



Normal load



DC diagnostic Short

Threshold selection = 00



Rdcsl



Shorted load



-



Rdcol



Open load



DC diagnostic Short

Threshold selection = 00



59



-



-







4.3



-



30.1







-



-



2.78







118



-



-







0.54



-



3.71







-



-



0.34







DC test - High Gain - Rsetting = Option 3

Rdcnl



Normal load



DC diagnostic short

threshold selection = 00



Rdcsl



Shorted load



-



Rdcol



Open load



DC diagnostic Short

Threshold selection = 00



DC test - High Gain - Rsetting = Option 4 (intended for low ohminc speakers)

Rdcnl



Normal load



DC diagnostic short

threshold selection = 00



Rdcsl



Shorted load



-



Rdcol



Open load



DC diagnostic short

threshold selection = 00



14.7



-



-







AC test - High Gain

Vac(2)



AC test output amplitude value



Single ended signal

Rac setting =Option 1



1.26



1.4



1.54



Vp



Vac(2)



AC test output amplitude value



Single ended signal

Rac setting = Option 2



2.53



2.8



3.07



Vp



Vac(2)



AC test output amplitude value



Single ended signal

Rac setting = Option 3



5.06



5.6



6.14



Vp



AC test - High Gain - Rsetting = Option 1

Zmeas(nl)



Normal load



-



-



-



8







Zmeas(ol)



Open load



-



30



-



-







AC test - High Gain - Rsetting = Option 2

Zmeas(nl)



Normal load



-



-



-



16







Zmeas(ol)



Open load



-



60



-



-







AC test - High Gain - Rsetting = Option 3

Zmeas(nl)



Normal load



-



-



-



32







Zmeas(ol)



Open load



-



120



-



-







Rev 1



15/61

60



Electrical specifications



FDA2100LV

Table 6. Diagnostics (continued)



Symbol



Parameter



Test condition



Min.



Typ.



Max.



Unit



Short to GND det. (over this

Power amplifier in Mute or

output current limit, the output is

play, one or more short

considered in short circuit to

circuits protection activated

GND)



30



-



-



mA



Short to Vs det. (over this output

current limit, the output is

considered in short circuit to VS)



-30



-



-



mA



-



-



-



±3



mA



-



Permanent diagnostics



Pgnd



Pvs



Pnop



Normal operation thresholds.

(Within these output current

limits, the output is considered

without faults)



Vo



Offset detection -



Output voltage (Gain High)



Vo



Offset detection



Output voltage (Gain Low)



4.3



-



V



2.2



-



V



Tph



Thermal protection junction

temperature



Gain attenuation of 60 dB



-



165



-



°C



Tpl



Thermal protection junction

temperature



Gain attenuation of 0.5 dB



-



155



-



°C



Tw1



Thermal warning junction

temperature



-



-



Tpl-5



-



°C



Tw2



Thermal warning junction

temperature



-



-



Tpl-20



-



°C



Tw3



Thermal warning junction

temperature



-



-



Tpl-35



-



°C



Fn



External thermal Sensor

Comparator Input normal

threshold value



Fn ≥ V(ExtTher)-V(AN-n)



1.9



-



-



V



Fw



External thermal sensor

comparator Input warning

threshold



Fw ≤ V(ExtTher)-V(AN-n)



-



-



1.4



V



Fh



External thermal sensor

comparator Input hysteresis



-



0.1



-



-



V



Vt



Comparator input test mode



-



0.2



-



0.6



V



1. Frequency digitally controlled by locking to



I 2S



clock.



2. Min/max test correlated to GV1, GV2 measurements.



16/61



Rev 1



FDA2100LV



Electrical specifications

Table 7. Step-up



Symbol



Parameter



Test condition



Min.



Typ.



Max.



Unit



1.4



1.55



1.7



V



Step-up

V(Comp)



I2C mode, v18 settled



Compensation pin voltage



2



V(Comp)



Compensation pin voltage



I C mode, v20 settled



1.55



1.7



1.95



V



V(Comp)



Compensation pin voltage



I2C mode, v22.5 settled



1.7



1.85



2



V



2



V(Comp)



Compensation pin voltage



I C mode, v25 settled and

legacy mode



1.85



2



2.15



V



V(Ilim)



Current limiting threshold

voltage(1)



V(I1-V(I2)



0.18



0.25



0.32



V



Vgdl



V gate drive low voltage



Isink = 0.5 A

Isink = 20 mA



-



-



2

0.1



V



Vgdh



V gate drive high voltage



Isource = 0.5 A

Isource = 20 mA



7

9



-



-



V



1. Applying this voltage to the pins I1, I2 the output voltage decreases, and the flag DB1-D7 must be set at 1.



Table 8. Interfaces

Symbol



Parameter



Test condition



Min.



Typ.



Max.



Unit



-



-



400



kHz



I2C bus interface

fSCL



Clock frequency



-



VIL



Input low voltage



-



-



-



0.8



V



VIH



Input high voltage



-



1.3



-



-



V



VOLMAX



Maximum low output voltage I2C

Isink = 3 mA

data



-



-



0.5



V



IOLMAX



Maximum low output current I2C

data



-



-



1



mA



ILIMAX



Maximum input leakage current



-



-



±1



µA



-



Enable 1,2,3

Venl



Input low voltage



-



-



-



1.5



V



Venh



Input high voltage



-



2.3



-



-



V



I2S bus interface

VIL-I2S



Input low voltage



-



-



-



0.8



V



VIH-I2S



Input high voltage



-



1.3



-



-



V



Rev 1



17/61

60



General introduction



3



FDA2100LV



General introduction

The FDA2100LV is a fully digital single chip class D amplifier with high immunity to the

demodulation filter effects, built-in diagnostic functions and step-up driver. The high

integration level and the on-board signal processing allow an excellent audio performance

to be achieved. Thanks to the digital input and a feedback strategy in the power stage that

make the amplifier robust with respect to the output filter non-idealities, the number and size

of the external components are minimized. A number of features were is also included to

reduce EMI, making the system compliant with the stringent limits typical of automotive

applications and the fully digital approach provides a strong GSM immunity.

The FDA2100LV includes digital I2C and I2S interfaces, internal 20 bits DAC conversion,

digital signal processing for interpolation and noise shaping, step-up driver, self diagnostic

functions and automatic detection of wrong load connections or variation of the load with

respect to the expected one, internal PLL for a pure clock generation.



3.1



New feedback topology

Differently from the typical PWM switching amplifiers, a new feedback technique is adopted

by FDA2100LV. The LC filter is included in the feedback loop making the amplifier highly

insensitive to the characteristics of such a demodulator group. This solution optimizes the

system performance in terms of THD and frequency response.

Regardless of the big phase shifting introduced by the output filter the device shows a great

phase margin for any load condition.

The system stability has been tested taking in account:





Spread process







PWM switching variation (from 300 to 440 kHz)







Silicon temperature variation (from -40 to 150 °C)







Load variation (both inductive and capacitive considered)







LC demodulator filter variation and tolerance







Voltage supply variation (from 6 to 35 V)



The system has been designed to guarantee a phase margin > 45 deg for any working

condition.

The new feedback topology assures a strong control of voltage and current across the load

making the diagnostic load detection reliable.



3.2



LC filter design

The audio performance of a Class D amplifier is heavily influenced by the characteristics of

the output LC filter. The choice of its components is quite critical because a lot of constraints

have to be fulfilled at the same time: size, cost, effective EMI filtering, efficiency.

In particular, both the inductor and the capacitor exhibit a non linear behavior: the value of

the inductance is a function of the instantaneous current in it and similarly the value of the

capacitor is a function of the voltage across it.



18/61



Rev 1



FDA2100LV



General introduction

In a classical approach, in which the feedback loop is closed right at the output of the power

stage, the LC filter is placed outside the loop and these nonlinearities cause the Total

Harmonic Distortion (THD) to increase. The only way to avoid this phenomenon would be to

use components which are highly linear, but this means they are also bigger and/or more

expensive.

Furthermore, when the LC filter is outside the loop, its frequency response heavily depends

on the impedance of the loudspeaker; this is one of the most critical aspects of Class-D

amplifiers. It can be mitigated, but not solved, by means of additional snubber networks,

increasing cost, volume and power dissipation.

The FDA2100LV proposes a novel strategy to include the output LC filter in the feedback

loop for Class D stages with pulse width modulation at fixed carrier in order to minimize the

effect of the filter itself on the global performances of the system.

However, since the demodulator group is now in the feedback path, some constraints

regarding the inductor and capacitor choice are still present but of course less stringent than

a typical switching application. For additional details, please refer to the Client Pack

documentation for further information.



3.3



Load possibilities

The FDA2100LV supports several load possibilities and configurations. Unless specified by

means of I2C bus communication, the default configuration is suitable for a 2 channels

application. By means I2C bus it is possible to choose a single channel solution with parallel

outputs.



Rev 1



19/61

60



Operation mode



4



FDA2100LV



Operation mode

The device has four main operation modes:





Standby mode







Legacy mode 1(in phase)







Legacy mode 2 (not in phase)







I2C mode



These operations are selected by the pins ENABLE1, ENABLE2 and ENABLE3 following

the next table:

Table 9. Operation mode

Operation



ENABLE1



ENABLE2



ENABLE3



Standby mode



0



0



0



Legacy mode 1 (in phase)



1



0



0



Legacy mode 2 (not in phase)



1



0



1



I2C mode address 1 - (1101000)



0



1



0



I



2C



mode address 2 - (1101001)



1



1



0



I



2C



mode address 3 -(1101010)



0



0



1



I



2C



mode address 4 - (1101011)



Reserved (test mode)



4.1



0



1



1



1



1



1



Standby mode

When the ENABLE1, ENABLE2, ENABLE3 pins are low the device is in standby mode. The

current consumption is ISB.



4.2



Legacy mode

With an appropriate selection of ENABLE1/2/3 it is possible to select two Legacy modes (in

phase/ not in phase). When either Legacy mode 1 or Legacy mode 2 is selected, the

I2C bus is disabled (it is not possible to send commands to the amplifier or to receive data

from device to the µP).(a)



4.3



I2C mode

Refer to Table 9 for the description of ENABLE1/2/3 combinations that bring device in

I2C bus mode, with addresses "1", "2", "3" and "4" respectively. In this way, 4 devices can be

easily used in a board with a single I2C bus.

When a valid combination of ENABLE1/2/3 is recognized, the device turns on the internal

supply voltage of the I2C interface (and after ~5ms becomes ready to be programmed).

The internal I2C registers are pre-settled in "default condition", waiting for the I2C next

instruction.



a. Although in legacy mode the I2C bus is not effective, the device recognizes the address with the acknowledge.



20/61



Rev 1



FDA2100LV



4.4



Operation mode



I2C functions

Several functions can be enabled/disabled by means of an I2C serial communication bus.

Here a simplified list of the main I2C options:





Step-up driver settings (ON/OFF, output voltage selection, clock dithering,







Soft start activation, auto-off function for high chip temperature)







Amplifier gain selection (high/low gain)







Power stage ON/OFF control channel by channel







Parallel outputs configuration







Slow/Fast play and mute functions







High pass filtering for the digital input signal







Woofer and tweeter mis-connections test settings







Low Radiation Mode (anti pulse-skipping function)







I2S / TDM 4/8 channels







44.1 kHz, 48 kHz, 96 kHz, 192 kHz word frame clock selection







PWM switching frequency selection







PWM and/or PLL clock dithering







Thermal warning selection







Mute/Unmute function







Under voltage warning events







LC filter output filter selection



Any detected fault condition will be reported by means I2C, included shorts event to Vdd,

GND and mixed mis-connections, over voltage, over-temperature, digital offset warning.

The FDA2100LV can work in slave mode only.



Rev 1



21/61

60



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Table 5. General and audio characteristics

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