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Figure 2. Pins connection diagram (top view)

Figure 2. Pins connection diagram (top view)

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Block diagram and pins description



FDA2100LV



Table 2. Pins list description

Pin #



Pin name



64



N.C.



63



Gnd1-



51-62



N.C.



50



Gnd2-



49



TAB



48



Feedback2-



47



Out2-



Channel 2 half bridge output -



46



Out2-



Channel 2 half bridge output -



45



Vdd2-



Channel 2 half bridge power supply -



44



Vdd2+



Channel 2 half bridge power supply +



43



Out2+



Channel 2 half bridge output +



42



Out2+



Channel 2 half bridge output +



41



Feedback2+



40



Gnd2+



39



N.C.



38



I2S-Clock



I2S/TDM clock Input



37



I2S-Sinc



I2S/TDM sinc Input



36



I2S-Data



I2S/TDM data Input



35



Test



Test pin (do not use)



34



I2C-Clock



I2C data Clock



33



I2C-Data



I2C data input



32



CD/DIAG



Clip detector and diagnostic output: over-current protection, thermal warning, offset

detection



31



Enable 2



Chip enable 2



30



Enable 1



Chip enable 1



29



PLL_Filter



PLL filter network



28



Mute



27



D-Gnd



Digital ground



26



Dig-P



Positive digital supply V(svr)+1.65 (internally generated)



25



Dig-N



Negative digital supply V(svr)-1.65 (internally generated)



24



ExtTher



External thermal protection input



23



IsetProt



Current protection resistor setting



22



SVR



Supply voltage ripple rejection capacitor



21



An-N



Negative analog supply V(svr)-1.65 (internally generated)



20



An-P



Positive analog supply V(svr)+1.65 (internally generated)



8/61



Function

Not connected

Channel 1, half bridge power ground Not connected

Channel 2, half bridge power ground TAB connection

Channel 2 half bridge feedback -



Channel 2 half bridge feedback +

Channel 2, half bridge power ground +

Not connected



Mute input (6 µA source current)



Rev 1



FDA2100LV



Block diagram and pins description

Table 2. Pins list description (continued)



Pin #



Pin name



Function



19



A-Gnd



Analog ground



18



D-Vdd



Digital power supply



17



A-Vdd



Analog power supply



16



Enable 3



15



I2



Step-up current limiting reference



14



I1



Step-up current limiting input



13



Comp



Step-up compensation input



12



Vbat



11



Gate-driver



10



SU-Gnd



Step-up power ground



9



Gnd1+



Channel 1, half bridge power ground +



8



Feedback1+



7



Out1+



Channel 1 half bridge output +



6



Out1+



Channel 1 half bridge output +



5



Vdd1+



Channel 1 half bridge power supply +



4



Vdd1-



Channel 1 half bridge power supply -



3



Out1-



Channel 1 half bridge output -



2



Out1-



Channel 1 half bridge output -



1



Feedback1-



Chip enable 3



Power supply (battery)

External PowerMOS gate drive output



Channel 1 half bridge feedback +



Channel 1 half bridge feedback -



Rev 1



9/61

60



Electrical specifications



FDA2100LV



2



Electrical specifications



2.1



Absolute maximum ratings

Table 3. Absolute maximum ratings



Symbol

Vop

Vpeak



Parameter



Test conditions



Operating supply voltage

Peak supply voltage

2



Value



Unit



RL = 4 Ω



30



V



RL = 8 Ω



35



V



t = 50 ms Max.



50



V



Vi2c



I C bus pins voltage



-



-0.3 to 4.6



V



Vi2s



I2S



bus pins voltage



-



-0.3 to 4.6



V



Enable 1,2



Enable pins voltage



-



-0.3 to 6



V



CD/DIAG



CD/DIAG pin



-



-0.3 to 6



V



30V Max.



7.2



A



35V Max.



4



A



-



200



kHz



-



55 to 150



°C



-



–40 to 105



°C



IO

Fs max

Tstg, Tj

Tamb



Output peak current (repetitive f > 10 Hz)(1)

Max. input sample rate

Storage and junction



temperature(2)



Operative temperature range



1. For internal current limitation value refer to Section 6.4.

2. A suitable heatsink should be used to keep Tj inside specified limits.



2.2



Thermal data

Table 4. Thermal data

Symbol

Rth j-case



2.3



Parameter

Thermal resistance junction-to-case



Max.



Value



Unit



2



°C



Electrical characteristics

Refer to the test circuit, Vdd = Vbatt = 14.4 V; RL = 4 Ω; f = 1 kHz; Tamb = 25 °C; unless

otherwise specified. Tested at Tamb = 25 °C and Thot = 105 °C; functionality guaranteed for

Tj = -40 °C to 150 °C. Fsample = 48 kHz; PWM 'in phase'; unless otherwise specified.

Table 5. General and audio characteristics



Symbol



Parameter



Test condition

RL = 2 Ω



Vdd, Vbatt



Supply voltage range



RL = 4 Ω



Typ.



Max.



Unit



6



-



18(1)



V



-



(1)



30



V



-



35(1)



V



6



RL = 8 Ω



10/61



Min.



6



Rev 1



FDA2100LV



Electrical specifications

Table 5. General and audio characteristics (continued)



Symbol



Parameter

2



2



Test condition



Min.



Typ.



Max.



Unit



I C, I S bus pins

voltage



-



-



-



3.6



V



Venable



Enable pins voltage



-



-



-



5.5



V



CD/Diag



CD/Diag pin voltage



-



-



-



5.5



V



Idvbatt



Total quiescent drain

current pin Vbatt



Device in standby condition



-



-



2



µA



Idvdd



Total quiescent drain

current pins Vdd



Device in standby condition



-



-



5



µA



Idvbatt



Total quiescent drain

current pin Vbatt



Device ON



-



32



40



mA



Idvdd



Total quiescent drain

current pins Vdd



Device ON



-



80



100



mA



RL = 4 Ω; max power Vdd = 15.2 V



42(2)



50(2)



-



W



THD = 10 %



23(2)



29(2)



-



W



RL = 2 Ω; THD 10 %



38(2)



50(2)



-



W



RL = 2 Ω; max power



57(2)



78(2)



-



W



Vdd: 25 V; max power



-



135(2)



-



W



Vdd: 25 V; THD = 10 %



72(2)



80(3)



-



W



Vdd: 30 V; THD = 10 %



100(2)



120(3)



-



W



Vdd: 30 V; max power



-



180(3)



-



W



Total harmonic

distortion



PO = 1 W to 10 W, f = 1 kHz



-



0.03



00.5



%



PO = 1 W to 10 W, f = 10 kHz



-



0.2



0.5



%



CT



Cross talk



f = 1 kHz to 10 kHz



60



80



-



dB



GV1



Voltage gain high



GAIN @ -10 dBFS

44.1-48 and 96 KHz

192 kHz



9.3

11.5



10.3

13



11.3

14.5



Vp



Voltage gain low



GAIN @ -10 dBFS

44.1-48 and 96 KHz

192 kHz



5.5

6.7



6

7.6



6.5

8.5



Vp



Voltage gain match



-



-1



-



1



dB



DR



Dynamic range



-



-



108



-



dB

Awtd(3)



EIN1



Output noise GV = GV1



A-wtd, no output signal



-



75



100



µV



SNR



Signal to noise ratio



A-wtd



-



110



-



dB

A-wtd



SVR



Supply voltage rejection f = 1 kHz; Vr = 1 Vpk;



60



85



-



dB



Mute pin source current -



3



6



9



µA



VI2C, VI2S



PO



THD



GV2

GV1,2



IM



Output power (2)



Rev 1



11/61

60



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Figure 2. Pins connection diagram (top view)

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