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4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10  (Extended) 

4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10  (Extended) 

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PIC16F87X
15.4

DC Characteristics: PIC16F873/874/876/877-04 (Extended)
PIC16F873/874/876/877-10 (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Operating voltage VDD range as described in DC specification
(Section 15.1)

DC CHARACTERISTICS
Param
No.

Sym

Characteristic

Min

Typ†

Max

Units

VOL

Output Low Voltage
I/O ports
OSC2/CLKOUT (RC osc config)
Output High Voltage







0.6
0.6

V
V

IOL = 7.0 mA, VDD = 4.5V
IOL = 1.2 mA, VDD = 4.5V







8.5

V
V
V

IOH = -2.5 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V
RA4 pin



15

pF

In XT, HS and LP modes when
external clock is used to drive
OSC1







50
400

pF
pF

100K
VMIN





5.5



4

8

1000
VMIN
VMIN






5.5
5.5

D080A
D083A
VOH
D090A
D092A
D150*

VOD

D100

COSC2

D101
D102

CIO
CB

D120
D121
D122
D130
D131
D132A

VDD - 0.7
I/O ports(3)
OSC2/CLKOUT (RC osc config) VDD - 0.7
Open Drain High Voltage

Capacitive Loading Specs on Output Pins
OSC2 pin


All I/O pins and OSC2 (RC mode)
SCL, SDA (I2C mode)
Data EEPROM Memory
ED Endurance
VDRW VDD for read/write
TDEW Erase/write cycle time
Program FLASH Memory
EP Endurance
VPR VDD for read
VDD for erase/write

D133
*


Conditions

E/W 25°C at 5V
V Using EECON to read/write
VMIN = min. operating voltage
ms
E/W 25°C at 5V
V VMIN = min operating voltage
V Using EECON to read/write,
VMIN = min. operating voltage
ms

TPEW Erase/Write cycle time

4
8
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.

DS30292C-page 160

 2001 Microchip Technology Inc.

PIC16F87X
15.5

Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS

3. TCC:ST

(I2C specifications only)

2. TppS

4. Ts

(I2C specifications only)

T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF

output access
Bus free

TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition

FIGURE 15-5:

T

Time

osc
rd
rw
sc
ss
t0
t1
wr

OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR

P
R
V
Z

Period
Rise
Valid
Hi-impedance

High
Low

High
Low

SU

Setup

STO

STOP condition

LOAD CONDITIONS
Load Condition 2

Load Condition 1
VDD/2

RL

CL

Pin

CL

Pin

VSS

VSS

RL

= 464 Ω

CL

= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports,
15 pF for OSC2 output

Note: PORTD and PORTE are not implemented on PIC16F873/876 devices.

 2001 Microchip Technology Inc.

DS30292C-page 161

PIC16F87X
FIGURE 15-6:

EXTERNAL CLOCK TIMING
Q4

Q1

Q2

Q3

Q4

Q1

OSC1
1

3

3

4

4

2
CLKOUT

TABLE 15-1:
Parameter
No.

EXTERNAL CLOCK TIMING REQUIREMENTS
Sym

Characteristic

FOSC External CLKIN Frequency
(Note 1)

Oscillator Frequency
(Note 1)

1

TOSC External CLKIN Period
(Note 1)

Oscillator Period
(Note 1)

2

TCY

Instruction Cycle Time
(Note 1)
TosL, External Clock in (OSC1) High or
TosH Low Time

Min

Typ†

Max

Units

DC
DC
DC
DC
DC
DC
0.1
4
4
5
250
250
100
50
5
250
250
250
100
50
5
200






















TCY

4
4
10
20
200
4
4
10
20
200






10,000

250
250

DC

MHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
kHz
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
ns

Conditions
XT and RC osc mode
HS osc mode (-04)
HS osc mode (-10)
HS osc mode (-20)
LP osc mode
RC osc mode
XT osc mode
HS osc mode (-10)
HS osc mode (-20)
LP osc mode
XT and RC osc mode
HS osc mode (-04)
HS osc mode (-10)
HS osc mode (-20)
LP osc mode
RC osc mode
XT osc mode
HS osc mode (-04)
HS osc mode (-10)
HS osc mode (-20)
LP osc mode
TCY = 4/FOSC

100


ns XT oscillator
2.5


µs LP oscillator
15


ns HS oscillator
4
TosR, External Clock in (OSC1) Rise or —

25
ns XT oscillator
TosF Fall Time


50
ns LP oscillator


15
ns HS oscillator
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at "min." values with an
external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time
limit is "DC" (no clock) for all devices.
3

DS30292C-page 162

 2001 Microchip Technology Inc.

PIC16F87X
FIGURE 15-7:

CLKOUT AND I/O TIMING
Q1

Q4

Q2

Q3

OSC1
11

10
CLKOUT
13
14

19

12

18

16

I/O Pin
(Input)
15

17
I/O Pin
(Output)

New Value

Old Value

20, 21
Note: Refer to Figure 15-5 for load conditions.

TABLE 15-2:
Param
No.

CLKOUT AND I/O TIMING REQUIREMENTS

Symbol

Characteristic

Min

Typ†

Max

Units Conditions

10*

TosH2ckL OSC1↑ to CLKOUT↓



75

200

ns

(Note 1)

11*

TosH2ck OSC1↑ to CLKOUT↑
H



75

200

ns

(Note 1)

100

ns

(Note 1)

12*
13*

TckR

CLKOUT rise time



35

TckF

CLKOUT fall time



35

100

ns

(Note 1)

14*

TckL2ioV CLKOUT ↓ to Port out valid





0.5TCY + 20

ns

(Note 1)

15*

TioV2ckH Port in valid before CLKOUT ↑

TOSC + 200





ns

(Note 1)

16*

TckH2ioI Port in hold after CLKOUT ↑

0





ns

(Note 1)

17*

TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid



100

255

ns

18*

TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)

Standard (F)

100





ns

Extended (LF)

200





ns

19*
20*

TioV2osH Port input valid to OSC1↑ (I/O in setup time)
TioR

Port output rise time

0





ns

Standard (F)



10

40

ns

Extended (LF)





145

ns

Standard (F)



10

40

ns

21*

TioF

Port output fall time





145

ns

22††*

Tinp

INT pin high or low time

TCY





ns

23††*

Trbp

RB7:RB4 change INT high or low time

TCY





ns

Extended (LF)

*


These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

 2001 Microchip Technology Inc.

DS30292C-page 163

PIC16F87X
FIGURE 15-8:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING

VDD
MCLR
30

Internal
POR
33
PWRT
Time-out

32

OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset

31

34

34

I/O Pins
Note: Refer to Figure 15-5 for load conditions.

FIGURE 15-9:

BROWN-OUT RESET TIMING

VBOR

VDD

35

TABLE 15-3:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS

Parameter
No.

Symbol

30

TmcL

MCLR Pulse Width (low)

2





µs

VDD = 5V, -40°C to +85°C

31*

Twdt

Watchdog Timer Time-out Period
(No Prescaler)

7

18

33

ms

VDD = 5V, -40°C to +85°C

Oscillation Start-up Timer Period



1024 TOSC





TOSC = OSC1 period

Power-up Timer Period

28

72

132

ms

VDD = 5V, -40°C to +85°C





2.1

µs

100





µs

Characteristic

32

Tost

33*

Tpwrt

34

TIOZ

I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset

35

TBOR

Brown-out Reset pulse width

*


Min

Typ†

Max

Units

Conditions

VDD ≤ VBOR (D005)

These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

DS30292C-page 164

 2001 Microchip Technology Inc.

PIC16F87X
FIGURE 15-10:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

RA4/T0CKI

41

40

42

RC0/T1OSO/T1CKI

46

45

47

48

TMR0 or
TMR1
Note: Refer to Figure 15-5 for load conditions.

TABLE 15-4:

TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param
No.

Symbol

40*

Tt0H

T0CKI High Pulse Width

41*

Tt0L

T0CKI Low Pulse Width

42*

Tt0P

T0CKI Period

45*

Tt1H

46*

Tt1L

47*

Tt1P

Characteristic

Min
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler

T1CKI High Time Synchronous, Prescaler = 1
Synchronous,
Standard(F)
Prescaler = 2,4,8 Extended(LF)
Asynchronous
Standard(F)
Extended(LF)
T1CKI Low Time Synchronous, Prescaler = 1
Synchronous,
Standard(F)
Prescaler = 2,4,8 Extended(LF)
Asynchronous
Standard(F)
Extended(LF)
T1CKI input
Synchronous
Standard(F)
period
Extended(LF)

Asynchronous

48
*


0.5TCY + 20
10
0.5TCY + 20
10
TCY + 40
Greater of:
20 or TCY + 40
N
0.5TCY + 20
15
25
30
50
0.5TCY + 20
15
25
30
50
Greater of:
30 OR TCY + 40
N
Greater of:
50 OR TCY + 40
N
60
100
DC

Typ† Max Units

Conditions















ns
ns
ns
ns
ns
ns

Must also meet
parameter 42

























ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Must also meet
parameter 47

Must also meet
parameter 42
N = prescale value
(2, 4,..., 256)

Must also meet
parameter 47

N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)

Standard(F)


ns
Extended(LF)


ns
Ft1
Timer1 oscillator input frequency range

200 kHz
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2TOSC
— 7TOSC —
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

 2001 Microchip Technology Inc.

DS30292C-page 165

PIC16F87X
FIGURE 15-11:

CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)

RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50

51
52

RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53

54

Note: Refer to Figure 15-5 for load conditions.

TABLE 15-5:
Param
No.
50*

CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)

Sym
TccL CCP1 and CCP2
input low time

Characteristic
No Prescaler
With Prescaler

51*

TccH CCP1 and CCP2
input high time

Typ† Max Units

0.5TCY + 20





ns

Standard(F)

10





ns

Extended(LF)

20





ns

0.5TCY + 20





ns

10





ns

No Prescaler
Standard(F)
With Prescaler

Min

Extended(LF)

20





ns

3TCY + 40
N





ns



10

25

ns

52*

TccP CCP1 and CCP2 input period

53*

TccR CCP1 and CCP2 output rise time

Standard(F)
Extended(LF)



25

50

ns

54*

TccF CCP1 and CCP2 output fall time

Standard(F)



10

25

ns

Extended(LF)



25

45

ns

*


Conditions

N = prescale
value (1, 4 or 16)

These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

DS30292C-page 166

 2001 Microchip Technology Inc.

PIC16F87X
FIGURE 15-12:

PARALLEL SLAVE PORT TIMING (PIC16F874/877 ONLY)

RE2/CS

RE0/RD

RE1/WR

65
RD7:RD0
62

64

63
Note: Refer to Figure 15-5 for load conditions.

TABLE 15-6:
Parameter
No.
62

63*

PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874/877 ONLY)
Symbol

Characteristic

Min Typ† Max Units

TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)

TwrH2dtI

WR↑ or CS↑ to data–in invalid (hold time) Standard(F)
Extended(LF)

64

65
*


TrdL2dtV

TrdH2dtI

RD↓ and CS↓ to data–out valid

RD↑ or CS↓ to data–out invalid

20
25







ns
ns

20





ns

35





ns







80
90

ns
ns

10



30

ns

Conditions

Extended
Range Only

Extended
Range Only

These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

 2001 Microchip Technology Inc.

DS30292C-page 167

PIC16F87X
FIGURE 15-13:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS
70
SCK
(CKP = 0)
71

72

78

79

79

78

SCK
(CKP = 1)

80

BIT6 - - - - - -1

MSb

SDO

LSb

75, 76
SDI

MSb IN

BIT6 - - - -1

LSb IN

74
73
Note: Refer to Figure 15-5 for load conditions.

FIGURE 15-14:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS
81
SCK
(CKP = 0)
71

72
79

73
SCK
(CKP = 1)
80
78

SDO

MSb

BIT6 - - - - - -1

LSb

75, 76
SDI

MSb IN

BIT6 - - - -1

LSb IN

74
Note: Refer to Figure 15-5 for load conditions.

DS30292C-page 168

 2001 Microchip Technology Inc.

PIC16F87X
FIGURE 15-15:

SPI SLAVE MODE TIMING (CKE = 0)

SS
70
SCK
(CKP = 0)

83
71

72

78

79

79

78

SCK
(CKP = 1)

80
MSb

SDO

LSb

BIT6 - - - - - -1

77

75, 76
SDI

MSb IN

BIT6 - - - -1

LSb IN

74
73
Note: Refer to Figure 15-5 for load conditions.

FIGURE 15-16:

SPI SLAVE MODE TIMING (CKE = 1)
82

SS

SCK
(CKP = 0)

70
83
71

72

SCK
(CKP = 1)
80

MSb

SDO

BIT6 - - - - - -1

LSb

75, 76
SDI

MSb IN

77
BIT6 - - - -1

LSb IN

74
Note: Refer to Figure 15-5 for load conditions.

 2001 Microchip Technology Inc.

DS30292C-page 169

PIC16F87X
TABLE 15-7:
Param
No.

SPI MODE REQUIREMENTS

Symbol

Characteristic
SS↓ to SCK↓ or SCK↑ input

Min

Typ†

Max

Units

Tcy





ns
ns

70*

TssL2scH,
TssL2scL

71*

TscH

SCK input high time (Slave mode)

TCY + 20





72*

TscL

SCK input low time (Slave mode)

TCY + 20





ns

73*

TdiV2scH,
TdiV2scL

Setup time of SDI data input to SCK edge

100





ns

74*

TscH2diL,
TscL2diL

Hold time of SDI data input to SCK edge

100





ns

75*

TdoR

SDO data output rise time




10
25

25
50

ns
ns

76*

TdoF

SDO data output fall time



10

25

ns

77*

TssH2doZ

SS↑ to SDO output hi-impedance

10



50

ns

78*

TscR

SCK output rise time (Master mode) Standard(F)
Extended(LF)




10
25

25
50

ns
ns

SCK output fall time (Master mode)



10

25

ns







50
145

ns

Tcy





ns





50

ns

1.5TCY + 40





ns

Standard(F)
Extended(LF)

79*

TscF

80*

TscH2doV,
TscL2doV

SDO data output valid after SCK
edge

81*

TdoV2scH,
TdoV2scL

SDO data output setup to SCK edge

82*

TssL2doV

SDO data output valid after SS↓ edge

83*

TscH2ssH,
TscL2ssH

SS ↑ after SCK edge

*


Standard(F)
Extended(LF)

Conditions

These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

FIGURE 15-17:

I2C BUS START/STOP BITS TIMING

SCL

93

91
90

92

SDA

START
Condition

STOP
Condition

Note: Refer to Figure 15-5 for load conditions.

DS30292C-page 170

 2001 Microchip Technology Inc.